THS3217 Datasheet, PDF (30/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
9.2 Functional Block Diagram
+VCC2
16
VMID_OUT
15
VREF
14
50 k
VMID_IN 1
100
x1
50 k
50
+IN 2 x1
+
250
500
±IN 3 x1
+VCC1
13
18.5 k
12 VIN±
11 VOUT
18.5 k
10 DISABLE
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PATHSEL 4
9 VIN+
5
±VCC2
6
VO1
7
GND
8
±VCC1
9.3 Feature Description
9.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2-V/V (Pins 2, 3, 6 and 14)
This buffered-amplifier stage isolates the DAC output nodes from the differential to single-ended conversion.
Presenting two high-impedance inputs allows the DAC to operate in its best configuration independent of
subsequent operations. The two very wideband input buffers hold an approximately constant response shape
over a wide input common-mode operating voltage. Figure 13 shows 6 dB of gain with 0.5-dB flatness through
500 MHz over the intended –1-to +3-V input common-mode range. In this case, the VREF pin is grounded,
forcing the D2S output to be centered on ground for any input common-mode voltage. For the D2S-only tests, a
100-Ω load is used to showcase the performance of this stage directly driving a doubly-terminated cable. The
wide input common-mode range of the D2S satisfies the required compliance voltage over a wide range of DAC
types. Most current sourcing DACs require an average dc compliance voltage on their outputs near ground.
Current sinking DACs require an average dc compliance voltage near their positive supply voltage for the analog
section. The 3-V maximum common-mode range is intended to support DAC supplies up to 3.3 V, where the
average output operating current pulls down from 3.3 V by the termination impedance from the supply. For
instance, a 20-mA tail current DAC must level shift from a 3.3-V bias on the output resistors down to 3 V or
lower. This DAC-to-THS3217 configuration requires at least a 300-mV dc level shift with half the tail current in
each side, implying a 30-Ω load impedance to the supply on each side of the 20-mA reference current.
The overriding limits to the input common-mode operating range are due to the input buffer headroom. Over
temperature, the D2S input headroom specification is 2 V to the negative supply and 1.5 V to the positive supply.
Therefore, operation at a 3-V input common-mode voltage requires at least a 4.5-V positive supply, where 5 V is
a more conservative minimum.
While DAC outputs rarely have any common-mode signal present (unless the reference current is being
modulated), the D2S does a reasonable job of rejecting input common-mode signals over frequency. Figure 17
shows the CMRR to decrease above 10 MHz. For current-sinking DACs coming from a positive supply voltage,
any noise on the positive supply looks like an input common-mode signal. Keeping the noise small at higher
frequencies reduces the possibility of feedthrough to the D2S output due to the decreasing CMRR at higher
frequencies. A current-sinking DAC uses pull-up resistors to the voltage supply to convert the DAC output current
to a voltage. Make sure that the DAC voltage supply has been properly decoupled through a ferrite bead and
capacitor, π-filter network similar to the supply decoupling for the THS3217 shown in Figure 90.
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