THS3217 Datasheet, PDF (53/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
10.1.1.1.2 Detailed Design Procedure
The THS3217 is well suited for high-speed, low-distortion arbitrary waveform generator (AWG) applications
commonly used in laboratory equipment. In this typical application, a high-speed, complementary-current-output
DAC is used to drive the D2S. The OPS of the THS3217 easily drives a 100-MHz, 2.5-V_PP signal into a matched
50-Ω load. When a larger output signal is required, consider using the THS3091 as the final driver stage.
A passive RLC filter is commonly used on DAC outputs to reduce the high-frequency content in the DAC steps.
The filtering between the DAC output and the input to the D2S reduces higher-order DAC harmonics from
feeding into the internal OPS path when the external input path is selected. Feedthrough between the internal
and external OPS paths increases with increasing frequency; however, the input filter rolls off the DAC
harmonics before the harmonics couple to VOUT (pin 10) through the deselected OPS signal path. Figure 96
shows an example of a doubly-terminated differential filter from the DAC to the THS3217 D2S inputs at pins 2
and 3.The DAC is modeled as two, fixed, 10-mA currents and a differential, ac-current source. The 10-mA dc
midscale currents set up the average common-mode voltage at the DAC outputs and D2S inputs at 10 mA × 25
Ω = 0.25 V_CM. The total voltage swing on the DAC outputs is 0 V to 0.5 V.
Complementary
Output DAC
10 mA
IDIFF
10 mA
49.9
49.9
72 nH
15 pF
72 nH
15 pF
12 pF 49.9
D2S Stage with input
capacitance included
IN+
2
2.4 pF
12 pF 49.9
3
2.4 pF
IN-
Figure 96. 200-MHz Butterworth Filter Between DAC and D2S Inputs
Some of the guidelines to consider in this filter design are:
1. The filter cutoff is adjusted to hit a standard value in the standard high-frequency, chip inductors kits.
2. The required filter output capacitance is reduced from the design value of 14.4 pF to 12 pF to account for the
D2S input capacitance of 2.4 pF, as reported in the D2S Electrical Characteristics table.
3. The capacitor at the DAC output pins must also be reduced by the expected DAC output pin capacitance.
The DAC output capacitance is often specified as 5 pF, but is usually much lower. Contact the DAC
manufacturer for an accurate value.
Figure 97 shows the TINA-simulated filter response for the input-stage filter. The low-frequency 34-dBΩ gain is
due to the 50-Ω differential resistance at the DAC output terminals. At 400 MHz, this filter is down 16 dB from the
50-Ω level; it is also very flat through 100 MHz.
35
30
25
20
15
10
5
0
1M
10M
100M
1G
Frequency (Hz)
D508
Figure 97. Simulated, Differential-Input Filter Response
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