THS3217 Datasheet, PDF (7/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
7.6 Electrical Characteristics: OPS
at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF = GND,
R_F = 249 Ω⁽¹⁾, R_G = 162 Ω, A_V = 2.5 V/V, OPS R_LOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input
selected (PATHSEL ≥ 1.3 V), and T_J ≈ 25˚C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT LEVEL
(2)
AC PERFORMANCE ⁽³⁾
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Bandwidth for 0.2-dB flatness
Slew rate⁽⁴⁾
Over- and undershoot
Rise and fall time
Settling time to 0.1%
2nd-order harmonic distortion (HD2)
3rd-order harmonic distortion (HD3)
Noninverting input voltage noise
V_OUT = 100 mV_PP, peaking < 1.0 dB
V_OUT = 5 V_PP
V_OUT = 5 V_PP
V_OUT = 5-V step
Input t_r = 1 ns, V_OUT = 5-V step
Input t_r = 1 ns, V_OUT = 5-V step
Input t_r = 1 ns, V_OUT = 5-V step
f = 20 MHz, V_OUT= 5 V_PP
f = 20 MHz, V_OUT= 5 V_PP
f > 200 kHz
950
500
110
5500
8%
1.1
5
–69
–73
3.2
MHz
C
MHz
C
MHz
C
V/µs
C
C
ns
C
ns
C
dBc
C
dBc
C
nV/√Hz
C
Noninverting input current noise
f > 200 kHz
2.8
pA/√Hz
C
Inverting input current noise
f > 200 kHz
30
pA/√Hz
C
Closed-loop ac output impedance
DC PERFORMANCE ⁽³⁾
Open-loop transimpedance gain⁽¹⁾
Closed-loop gain
INPUT
f = 20 MHz
V_OUT = ±1 V, R_LOAD= 500-Ω
0.1% external R_F and R_G resistors
0.40
Ω
C
600
1200
kΩ
A
2.495
2.515
2.53 V/V
A
T_J = 25°C
External input offset voltage (pin 9 to
pin12)
T_J = 0°C to 70°C
T_J = –40°C to +125°C
External input offset voltage drift (pin
9 to pin12)
T_J = –40°C to +125°C
–12
±2.5
–20
–31
12 mV
A
17 mV
B
24 mV
B
-45
–115
–190 µV/°C
B
Internal input offset voltage (pin 6 to
pin 12)
Internal input offset voltage drift (pin
6 to pin 12)
T_J = 25°C
T_J = 0°C to 70°C
T_J = –40°C to +125°C
T_J = –40°C to +125°C
–12
±2.5
–23
–35
12 mV
A
18 mV
B
27 mV
B
–70
–150
–235 µV/°C
B
External to internal input offset
voltage match
T_J = 25°C
±1.2
mV
C
External noninverting input bias
current (pin 9)⁽⁵⁾
External noninverting input bias
current drift (pin 9)
T_J = 25°C
T_J = 0°C to 70°C
T_J = –40°C to +125°C
T_J = –40°C to +125°C
–5
±5
15
µA
A
–5.2
15.4
µA
B
–5.6
15.9
µA
B
–3
3
9 nA/°C
B
Inverting input bias current – either
input selected⁽⁵⁾
Inverting input bias current drift
T_J = 25°C
T_J = 0°C to 70°C
T_J = –40°C to +125°C
T_J = –40°C to +125°C
–40
–51
–65
–250
±5
–120
40
µA
A
46
µA
B
56
µA
B
–10 nA/°C
B
(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω R_F and 162-
Ω R_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.
(3) Output measured at pin 11.
(4) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f_–3dB.
(5) Currents out of pin treated as a positive polarity.
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