THS3217 Datasheet, PDF (32/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
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Feature Description (continued)
The IN+ buffer output drives a 150-Ω load with VREF grounded. Any source driving VREF must have the ability
to drive a 150-Ω load with low output impedance across frequency. For differential input signals, the IN– buffer
drives a 150-Ω active load. The active load is realized by a combination of the 250-Ω R_G resistor and the inverted
and attenuated signal present at the inverting terminal of the difference amplifier stage. If only IN– is driven (with
IN+ at a dc fixed level), the load is 250 Ω.
The resistor values around the D2S difference amplifier are derived in the following sequence, as shown in
Figure 77:
1. Select the feedback resistor value to set the response shape for the wideband CFA stage. The 500-Ω design
used here was chosen as a compromise between loading and noise constraints.
2. Set the input resistor on the inverting input side to give the desired single-sided gain for that path. Setting
R_G= 250-Ω results in a gain of –2 V/V from the buffered signal (–V) to the output of the difference amplifier.
3. Solve the required attenuation to the noninverting input to get a matched gain magnitude for the signal
provided at the buffer output (+V) on the noninverting path. If α = R2 / (R1 + R2), as shown in Figure 77,
then the solution for α is shown in Equation 2:
§
D _¨1
R_F
·
¸
2
© ^RG ¹
(1)
D²
R1
3 R1 R2
(2)
RG
250
-V
RF
500
.Â(+V)
VO1
+
R1
+V
R2
Figure 77. D2S Impedance Analysis
4. After solving the attenuation from the buffer output to the amplifier noninverting input, set the impedance (R1
+ R2). It is preferable to have the two first stage buffer outputs drive the same load impedance to match
nonlinearity in their outputs in order to improve even-order harmonic distortion. The load impedance from –V
to R_G has an active impedance because of the inverted and attenuated version of the input signal appearing
at the inverting amplifier node from the +V input signal. Assuming a positive input signal into the +V path, an
attenuated version of the signal appears at the amplifier summing junction side of R_G, while the inverted
version of the signal appears on the input side of R_G.
The impedance seen at node –V in Figure 77 is derived in Equation 3 by solving for the V/I expression across
R_G.
Z_i
R_G
1D
250
12
150
3
(3)
For load balancing, (R1 + R2) = 150 Ω while the attenuation is α. More generally, all the terms are now available
to solve for R2, as shown in Equation 4:
2
R2
R_G
D
D1
250 ³
12
3
(4)
R1 is then simply (Z_i- R2) = 50 Ω.
32
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