THS3217 Datasheet, PDF (14/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
www.ti.com
Typical Characteristics: D2S Only (continued)
at +V_CC = 6.0 V, –V_CC = –6.0 V, fixed gain of 2 V/V, 25-Ω D2S source impedance, V_IC = 0.25 V, external path selected
(PATHSEL = +V_CC), V_REF = GND, and D2S R_LOAD = 100 Ω at pin 6 (unless otherwise noted)
20
10
15
7
5
10
3
5
2
0
-5
-10
-15
-20
-25
-30
-55 -35 -15 5 25 45 65 85 105 125
Junction Temperature (qC)
D019
30 units shown
1
0.7
0.5
0.3
0.2
0.1
1M
10M
Frequency (Hz)
r4 V
r5 V
r6 V
r7.5 V
100M
D020
Figure 19. Output DC Offset Voltage vs Die Temperature
1.2
1
100 :
0.8
200 :
0.6
500 :
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
20 30 40 50 60 70 80 90 100 110 120 130 140
Time (ns)
D021
±1-V output pulse
Figure 20. Output Impedance vs Supply Voltage
1.1
100 :
200 :
500 :
1
0.9
0.8
Time (1 ns/div)
D022
±1-V output pulse
Figure 21. Large-Signal Step Response vs Load Resistance
1
Figure 22. Large-Signal Pulse Settling Response vs Load
Resistance
70
65
0
60
-1
55
-2
50
-3
-4
-5
1M
0.1 Vpp
0.25 Vpp
0.5 Vpp
1 Vpp
2 Vpp
10M
100M
Frequency (Hz)
25-Ω D2S source impedance on each input
1G
D023
45
40
35
30
10k
V_CM = -1 V, PSRR+
V_CM = -1 V, PSRR-
V_CM = 0 V, PSRR+
V_CM = 0 V, PSRR-
V_CM = 3 V, PSRR+
V_CM = 3 V, PSRR-
100k
1M
Frequency (Hz)
10M
D024
Figure 23. VREF Input Pin Frequency Response
Figure 24. Simulated Power-Supply Rejection Ratio vs Input
Common-Mode Voltage
14
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