THS3217 Datasheet, PDF (31/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
Feature Description (continued)
The D2S provides a differential gain of 6 dB. The gain is reasonably precise using internal resistor matching with
extremely low gain drift over temperature (see Figure 61 and Figure 62). The single-ended D2S output signal can
be placed over a wide range of dc offset levels using the VREF pin. The VREF pin shows a precise gain of 1 V/V
to the D2S output. Grounding VREF places the first stage output centered on ground (with some offset voltage).
For best ac performance through the D2S, anything driving the VREF pin must have a very wide bandwidth with
very low output impedance over frequency while driving a 150-Ω load. The on-chip midscale buffer provides
these features (see Figure 51). When a dc offset (or other small-level ac signal) must be applied to the VREF
pin, buffer the signal through the midscale buffer stage. Maintain the total range of the dc offset plus signal swing
within the available output swing range of the D2S. The headroom to the supplies is a symmetric ±1.65 V (max)
over temperature. Therefore, on the minimum ±4-V supply, the D2S operates over a ±2.35-V output range. At the
maximum ±7.9-V supply, a ±6.25-V output range is supported. At the higher swings, account for available linear
output current, including the current into the internal feedback resistor load of approximately 500-Ω.
Figure 76 shows the internal structure of the D2S functional block. It consists of two internal stages:
1. The first stage consists of two wideband, closed-loop, fixed gain of 1 V/V buffers to isolate the requirements
of the complementary DAC output from the difference operation of the D2S.
2. The second stage is a wideband CFA configured as a difference amplifier, operating in a fixed gain of 2 V/V,
performing the differential to single-ended conversion.
Complementary
Output DAC
10 mA
IDIFF
10 mA
RG
RF
250
500
3 x1
25
V_IN
+
R1
50
2 x1
R2
25
100
VO1 = 2VIN
6
14
Optional DC
Source
Figure 76. D2S Operating Example
The CFA design offers the best, full-power bandwidth versus supply current, with moderate noise and dc
precision. Figure 76 shows a typical current-sourcing DAC with a 20-mA total tail current. The tail current is split
equally between the 25-Ω termination resistors to produce a dc common-mode voltage and a differential ac
current signal. This example sets the input common-mode voltage at 0.25 V, and is also the compliance voltage
of the DAC. The 25-Ω termination resistors shown here are typically realized as a 50-Ω matched reconstruction
(or Nyquist) filter between the DAC and the THS3217 buffer inputs for most AWG applications. The DAC signal
is further amplified by 6 dB in the second stage for a net transimpedance gain of 100-Ω to the D2S output at
VO1. This configuration produces a 2-V_PP output for the 20-mA reference current assumed in the example of
Figure 76. The input common-mode voltage is cancelled on the two sides of the op amp circuit to give a ground
referenced output. Any voltage applied to the VREF pin has a gain transfer function of 1 V/V to VO1,
independent of the signal path, as long as the source impedance of VREF is very low at dc and over frequency.
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