THS3217 Datasheet, PDF (48/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
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Device Functional Modes (continued)
9.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
The simplest modification to this starting configuration is using the midscale buffer to drive the VREF pin with
either a dc or ac source into VMID_IN (pin 1), shown in Figure 91.
Ferrite
Bead
6V
VMID_OUT
16
15
+
± ^VMID_IN
1
50 k
2 x1
50 k
x1
50
49.9
Differential
V_IN
+
250
500
3 x1
49.9
14
100
4
5
6
7
200
Ferrite
Bead
13
18.5 k
18.5 k
162
12
249
49.9
11
AV = 5 V/V
To
50-Ÿ /RDG
10
9
8
±6 V
Figure 91. Differential to Single-Ended, Gain of 5-V/V Configuration With VREF Driven by the Midscale
Buffer
The VREF input can be used to offset the output of the D2S that will then be amplified by the OPS. The total dc
offset at the output of the OPS can also be corrected by adjusting the voltage at VMID_IN (pin 1). The on-chip
midscale buffer can be used as a low-impedance source to drive the correction voltage to the VREF pin. A
wideband small-signal source can also be summed into this path with a gain of 1 V/V to the D2S output pin.
Figure 49 shows the midscale buffer to have an extremely flat response through 100 MHz for < 100-mV_PPswings,
while 1 V_PP can be supported through 80 MHz with a flat response.
From this point on, the diagrams are simplified to not show the power-supply elements. However, the supplies
are required by any application, as described in the Application and Implementation section.
48
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