THS3217 Datasheet, PDF (59/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
10.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
VMID_OUT
7.5 V
VO1
7.5 V
VMID_IN = ±2 V ⁺
±
1 V_PP
49.9
49.9
16
15
1
50 k
2 x1
50 k
x1
50
+
250
500
3 x1
14
100
13
18.5 k
54.9
12
221
11
AV = ±4 V/V
VMID_OUT ±4 V
10
18.5 k
VPATHSEL > 1.3V
4
9
VMID_OUT
5
6
7
8
±7.5 V
VO1= VMID_OU T ±1 V
±7.5 V
Figure 104. Adding an Output DC Offset Using the Midscale Buffer
10.1.1.4.1 Design Requirements
An easy way to insert a dc offset into the signal channel (without sacrificing any of the DAC dynamic range) is to
apply the desired offset at VMID_IN and use it to bias VREF (pin 14) and VIN+ (pin 9). An example is shown in
Figure 104. This example shows a relatively low maximum differential input of 1 V_PP on any compliance voltage
required by the DAC. Other configuration options include:
1. The D2S output is offset using a dc input at VMID_IN (pin 1). Although shown here as ±2 V, the dc offset
expands to ±3.5 V when using ±7.5-V supplies.
2. Connecting VMID_OUT to the VREF input places the D2S output at the dc offset voltage along with a gain of
2 V/V version of the differential input voltage. The stated range of ±2 V, along with the ±0.5 V out of the
upper input buffer, requires a peak output current from VMID_OUT of 2.5 V / 150 Ω = 16.7 mA. This value is
well below the rated minimum linear output current of 40 mA.
3. The dc offset voltage is then applied to the external OPS input. Connecting the circuit in this manner results
in no additional dc gain between the D2S and OPS outputs, while it continues to retain the signal gain of the
OPS configured as an inverting amplifier. The values of R_F and R_G in this application example are derived
from Table 4. The OPS is setup for a gain of –4 V/V in this example. Using the resistor values from Table 4
results in the widest bandwidth for the OPS; however, the R_G = 54.9 Ω resistor presents a heavy load to the
D2S output. In such cases, scaling up the resistors in the OPS helps reduce the loading on the D2S output
at the expense of reduced OPS bandwidth.
4. No filtering is shown in this example; however, introducing filtering in the OPS R_G path is certainly possible.
In such cases, the R_G element is also the filter termination resistor. Any filtering adds some insertion loss that
can be recovered in the OPS stage.
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