THS3217 Datasheet, PDF (45/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
9.3.3.4 Driving Capacitive Loads
The OPS can drive heavy capacitive loads very well as shown in Figure 43 to Figure 48. All high-speed
amplifiers benefit from the addition of an external series resistor to isolate the load capacitor from the feedback
loop. Not having the series isolation resistor often leads to response peaking and possibly oscillation. If
frequency response flatness under capacitive load is the design goal, all CFA type amplifiers benefit by operating
with slightly higher R_F values. Targeting a slightly higher feedback transimpedance increases the nominal phase
margin before the capacitive load acts to decrease it. Using a higher RF value has the effect of achieving good
flatness across a range of capacitive loads using lower external series resistor values. Although the suggested
R_F and R_G values of Table 7 apply when driving a 100-Ω load, if the intended load is capacitive (for example, a
passive filter with a shunt capacitor as the first element, another amplifier, or a Piezo element), use the values
reported in Table 7 as a starting point. The values in Table 7 were used to generate Figure 43 and Figure 44.
The results come from a nominal total feedback transimpedance target of 405 Ω (versus 351 Ω used for
Table 4), and includes the internal 18.5-kΩ resistor in the design. Table 7 finds the least error to target gain in
the selection of standard resistor values, and limits the minimum R_G to 20 Ω. The gains calculated here put 18.5-
kΩ in parallel with the reported external standard value R_F.
TARGET GAIN
(V/V)
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Table 7. Suggested R_F and R_G Over Gain When Driving a Capacitive Load
BEST R_F
(Ω)
BEST R_G (Ω)
CALCULATED GAIN
(V/V)
(dB)
GAIN ERROR
(%)
348
681
1.501
3.529
0.077
332
324
2.011
6.070
0.575
309
205
2.491
7.927
–0.361
287
143
2.987
9.506
–0.420
267
105
3.520
10.930
0.565
249
82.5
3.992
12.024
–0.200
226
63.4
4.535
13.131
0.776
205
51.1
4.979
13.943
–0.419
178
39.2
5.505
14.815
0.085
158
31.6
5.961
15.506
–0.652
137
24.9
6.460
16.204
–0.621
121
20.0
7.004
16.907
0.058
130
20.0
7.451
17.444
–0.652
140
20.0
7.948
18.005
–0.652
154
20.5
8.457
18.544
–0.509
162
20.0
9.041
19.124
0.452
174
20.5
9.426
19.486
–0.780
182
20.0
10.034
20.030
0.341
As the capacitive load or amplifier gain increases, lower series resistor values can be used to hold a flat
response (see Figure 43). See Figure 44 for the measured SSBW shapes for various capacitive loads configured
with the suggested series resistor from the output of the OPS and the R_F and R_G values suggested in Table 7 for
a gain of 2.5 V/V. This measurement includes a 200-Ω shunt resistor in parallel with the capacitive load as a
measurement path.
Figure 45 and Figure 46 demonstrate the OPS harmonic distortion performance when driving a range of
capacitive loads. These show suitable performance for large-signal, piezo-driver applications. If voltage swings
higher than 12 V_PP are required, consider driving the OPS output into a step-up transformer. The high peak-
output current for the OPS supports very fast charging edge rates into heavy capacitive loads, as shown in the
step response plots (see Figure 47 and Figure 48). This peak current occurs near the center of the transition time
driving a capacitive load. Therefore, the I × R drop to the capacitive load through the series resistor is at a
maximum at midtransition, and back to zero at the extremes (low dV/dT points).
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