THS3217 Datasheet, PDF (58/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
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4. The D2S output is dc biased at midsupply and delivers two times the differential swing applied at its inputs.
Assuming 2 V_PP at the D2S inputs implies 4 V_PP at the D2S output pins. Lower input swings are supported
with the gain in the OPS adjusted to meet the desired output maximum.
5. The filter in Figure 103 is a 0.2-dB ripple, second-order Chebyshev filter at 15 MHz. If the desired maximum
frequency is 12 MHz, for instance, this filter is attenuating the HD2 and HD3 out of the D2S by approximately
3 dB and 5 dB, respectively. Increased attenuation can be provided with higher-order filters, but this simple
filter does a good job of band-limiting the high-frequency noise from the D2S outputs before the noise gets
into the OPS stage.
6. The dc bias voltage at VO1 drives a small dc current into the 18.5-kΩ resistor to ground at the OPS external
input, VIN+ (pin 9). The error voltage due to the bias current will level-shift the dc voltage at the OPS
noninverting input through the 105-Ω filter resistor. This offset will be amplified by the OPS gain since its R_G
element is referenced to the V_MID output with a dc gain of 3.4 V/V.
7. The logic lines are still referenced to ground in this single-supply application. The external path to the OPS is
selected by connecting PATHSEL (pin 4) to +V_CC. DISABLE (pin 10) is grounded in this example in order to
hold the OPS on. If the disable feature is required by the application, drive the OPS using a standard logic
control driver. Note that the midscale buffer output still drives R_G and R_F to midsupply in this configuration
with the OPS disabled.
8. The R_G element can be ac coupled to ground through a capacitor to operate at midsupply. Figure 103 shows
the midscale buffer driving R_G, thus eliminating the need for an added capacitor. Using a blocking capacitor
moves the dc gain to 1 V/V. The voltage on the external, noninverting input of the OPS sets the dc operating
point. Use of a blocking capacitor also lightens the load on the midscale buffer output, and eliminates the
bias on R_G when the OPS is disabled.
9. Piezo element drivers operate in a relatively low-frequency range; therefore, the OPS R_F is scaled up even
further than the values suggested in Table 7. An increased R_F allows R_G to also be scaled up, thereby
reducing the load on the midscale buffer, and allow a lower series output resistor to be used into the 300-pF
capacitive load.
10. The peak charging current into the capacitive load occurs at the peak dV/dT point. Assuming a 12-MHz
sinusoid at 12 V_PP requires a peak output current from the OPS of 6 V_PEAK × 2π × 12 MHz × 300 pF = 135
mA. This result matches the rated minimum peak output current of the OPS.
Using a very low series resistor limits the waveform distortion due to the I × R drop at the peak charging point
around the sinusoidal zero crossing. The 135 mA through 3.3 Ω causes a 0.45-V peak drop to the load
capacitance around zero crossing. The voltage drop across the series output resistor increases the apparent
third harmonic distortion at the capacitive load. Figure 45 and Figure 46 show 10-V_PP distortion sweeps into
various capacitor loads. The results shown in these figures are for the OPS only because the results set the
harmonic distortion performance in this example.
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