THS3217 Datasheet, PDF (63/73 Pages) Texas Instruments – THS3217 DC to 800-MHz, Differential-to-Single-Ended, DAC Output Amplifier

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12 Layout
THS3217
SBOS766B – FEBRUARY 2016 – REVISED FEBRUARY 2016
12.1 Layout Guidelines
High-speed amplifier designs require careful attention to board layout in order to achieve the performance
specified in the data sheets. Poor layout techniques can lead to increased parasitics from the board and external
components resulting in suboptimal performance, and also instability in the form of oscillations. The THS3217
evaluation module (EVM) serves as a good reference for proper, high-speed layout methodology. The EVM
includes numerous extra elements needed for lab characterization, and also additional features that are useful in
certain applications. These additional components can be eliminated on the end system if not required by the
application. General suggestions for the design and layout of high-speed, signal-path solutions include:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O
pins should be opened on all of the ground and power planes around those pins. On other areas of the board
continuous ground and power planes are preferred for signal routing with matched impedance traces for
longer runs.
2. Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins.
Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and
shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that
offer a much higher self-resonance frequency over standard capacitors. Avoid narrow power and ground
traces to minimize inductance between the pins and the decoupling capacitors. Follow the power-supply
guidelines recommended in the Power Supply Recommendations section.
3. Careful selection and placement of external components preserve the high-frequency performance of the
THS3217. Use low-reactance type resistors. Surface-mount resistors work best, and allow a tighter overall
layout. Keep the printed circuit board (PCB) trace length as short as possible. Never use wire-bound type
resistors in a high-frequency application. The output pin and inverting input pins are the most sensitive to
parasitic capacitance; therefore, always position the feedback and series output resistors, if any, as close as
possible to the inverting input pins and output pins. Place other network components, such as input
termination resistors, close to the gain-setting resistors.
4. When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces. On differential lines, like those on the D2S inputs, match the routing in order to
minimize common-mode noise effects and improve HD2 performance.
5. The input summing junction of the OPS is very sensitive to parasitic capacitance. Connect the R_G element
into the summing junction with minimal trace length to the device pin side of the resistor. The other side of
R_G can have more trace length if needed to the source or to ground. For best results, do not socket a high-
speed part like the THS3217. The additional lead length and pin-to-pin capacitance introduced by the socket
can create an extremely troublesome parasitic network that can make it almost impossible to achieve a
smooth, stable frequency response. Best results are obtained by soldering the THS3217 directly onto the
board.
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