DS90UH948-Q1 Datasheet, PDF (79/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Time (100 ps/DIV)
Figure 51. Loop-through CML Output at 2.6 Gbps Serial
Line Rate
Figure 52. OpenLDI Clock and Data Output at 74.25 MHz
Pixel Clock
10 Power Supply Recommendations
This device provides separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description table provide guidance on which circuit blocks are connected to which power pin pairs.
In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
10.1 Power Up Requirements and PDB Pin
When power is applied, power from the highest voltage rail to the lowest voltage rail on any of the supply pins.
For 3.3V IO operation, VDDIO and VDD33 can be powered by the same supply and ramped simultaneously. The
power supply ramp (VDD12, VDD33, and VDDIO) should be faster than 1.5ms with a monotonic rise. A large
capacitor on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the
recommended operating voltage. When PDB pin is pulled up to VDD33, a 10 kΩ pull-up and a >10 μF capacitor
to GND are required to delay the PDB input signal rise. All inputs must not be driven until both VDD33 and
VDDIO has reached steady state. Pins VDD33_A and VDD33_B should both be externally connected, bypassed,
and driven to the same potential (they are not internally connected).
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
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