DS90UH948-Q1 Datasheet, PDF (4/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
6 Pin Configurations and Functions
NKD
64-Pin WQFN
Top View
www.ti.com
CAP_PLL0 ⁴⁹
MODE_SEL1 ⁵⁰
VDDP12_CH0 ⁵¹
VDDR12_CH0 ⁵²
RIN0+ ⁵³
RIN0- ⁵⁴
CMF 55
VDD33_A 56
VDDR12_CH1 57
RIN1+ 58
RIN1- 59
VDDP12_CH1 60
MODE_SEL0 61
CMLOUTP 62
CMLOUTN 63
CAP_PLL1 64
DS90UH948-Q1
64 WQFN
Top Down View
DAP
32 VDDP12_LVD
31 VDD33_B
30 D4-
29 D4+
28 D5-
27 D5+
26 D6-
25 _D6+
24 _CLK2-
23 CLK2+
22 _D7-
21 _D7+
20 _{VDD12_LVD0}
19 _{D_GPIO0/MOSI}
18 _{D_GPIO1/MISO}
17 D_GPIO2/SPLK
Pin Functions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
FPD-LINK OPENLDI OUTPUT PINS - Layout note: for unused LVDS outputs, terminate with a single external 100 Ω termination at
the end of the transmission line.
CLK1-
CLK1+
37
O, LVDS Clock Differential Output
36
This pair requires an external 100 Ω termination for LVDS
CLK2-
CLK2+
24
O, LVDS Clock Differential Output
23
This pair requires an external 100 Ω termination for LVDS
D0-
43
O, LVDS Channel 0 Differential Output
D0+
42
This pair requires an external 100 Ω termination for LVDS
D1-
41
O, LVDS Channel 1 Differential Output
D1+
40
This pair requires an external 100 Ω termination for LVDS
D2-
39
O, LVDS Channel 2 Differential Output
D2+
38
This pair requires an external 100 Ω termination for LVDS
D3-
35
O, LVDS Channel 3 Differential Output
D3+
34
This pair requires an external 100 Ω termination for LVDS
D4-
30
O, LVDS Channel 4 Differential Output
D4+
29
This pair requires an external 100 Ω termination for LVDS
D5-
28
O, LVDS Channel 5 Differential Output
D5+
27
This pair requires an external 100 Ω termination for LVDS
4
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: DS90UH948-Q1