DS90UH948-Q1 Datasheet, PDF (6/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
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Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
PDB
48
I, LVCMOS Power-Down Mode Input Pin
Configuration PDB = 1, device is enabled (normal operation)
Pin w/ weak PDB = 0, device is powered down.
internal PD When the device is in the POWER DOWN state, the LVCMOS outputs are in tri-state,
the PLL is shutdown and IDD is minimized.
Note: PDB pin requires minimum ramp time of 200us
BISTEN
5
I, LVCMOS Bist Enable Pin
Configuration 0: BIST Mode is disabled.
Pin w/ weak _{1: BIST Mode is enabled.}
internal PD _{See Built-In Self Test (BIST) for more information}
BISTC
(INTB_IN)
4
I, LVCMOS Bist Clock Select.
Configuration _{0: PCLK}
Pin w/ weak _{1: 33MHz}
internal PD _{(Pin is shared with INTB_IN)}
INTB_IN
(BISTC)
4
I, LVCMOS Interrupt input.
w/ weak (Pin is shared with BISTC)
internal PD
BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS (default pin function) - Layout note: for unused GPIO(s), tie to an external
pulldown
GPIO0
(SDOUT)
7
Multi-function BCC GPIO0.
pin
default state: logic LOW
I/O,
(Pin is shared with SDOUT)
LVCMOS
GPIO1
(SWC)
8
Multi-function BCC GPIO1.
pin
default state: logic LOW
I/O,
(Pin is shared with SWC)
LVCMOS
GPIO2
(I2S_DC)
10
Multi-function BCC GPIO2.
pin
default state: logic LOW
I/O,
(Pin is shared with I2S_DC)
LVCMOS
GPIO3
(I2S_DD)
9
Multi-function BCC GPIO3.
pin
default state: logic LOW
I/O,
(Pin is shared with I2S_DD)
LVCMOS
HIGH-SPEED GPIO PINS HIGH-SPEED GPIO PINS (default pin function) - Layout note: for unused D_GPIO(s), tie to an external
pulldown
D_GPIO0
(MOSI)
19
I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode
default state: tri-state
(Pin is shared with MOSI)
D_GPIO1
(MISO)
18
I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode
default state: tri-state
(Pin is shared with MISO)
D_GPIO2
(SPLK)
17
I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode
default state: tri-state
(Pin is shared with SPLK)
D_GPIO3
(SS)
16
I/O, LVCMOS General Purpose I/O in 2-lane FPD-Link III mode
default state: tri-state
(Pin is shared with SS)
REGISTER READ/WRITES ONLY GPIO PINS (default pin function) - Layout note: for unused GPIO(s), tie to an external pulldown
GPIO5_REG
(I2S_DB)
11
Multi-function General Purpose Input/Output 5
pin
I2C register control only.
I/O, LVCMOS default state: logic LOW
(Pin is shared with I2S_DB)
GPIO6_REG
(I2S_DA)
12
Multi-function General Purpose Input/Output 6
pin
I2C register control only.
I/O, LVCMOS default state: logic LOW
(Pin is shared with I2S_DA)
6
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