DS90UH948-Q1 Datasheet, PDF (17/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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Timing Diagrams and Test Circuits (continued)
DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
PDB
VIH(min)
RIN[1:0]±
LOCK
t_DDLT
TRI-STATE
Figure 6. CML PLL Lock Time
RIN[1:0]+
VTL
VCM
VTH
RIN[1:0]-
VOH(min)
GND
Figure 7. FPD-Link III Receiver DC V_TH/V_TL Definition
I2S_CLK,
MCLK
I2S_WC,
I2S_D[D:A]
V_OHmin
V_OLmax
t_ROS
1/2 V_DDIO
t_ROH
V_DDIO
GND
V_DDIO
GND
Figure 8. Output Data Valid (Setup and Hold) Times
D[7:0]±
CLK[1:0]±
(Differential)
80%
20%
t_LVLHT
t_LVHLT
Figure 9. Input Transition Times
+VOD
0V
-VOD
D[7:0]+
CLK[2:1]+
D[7:0]-
CLK[2:1]-
(D[7:0]+) -
(D[7:0]-) or
(CLK[2:1]+) -
(CLK[2:1]-)
VOD+
VOD-
VOS
VOD+
VODp-p
0V
VOD-
Figure 10. FPD-Link Single-Ended and Differential Waveforms
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