DS90UH948-Q1 Datasheet, PDF (37/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
8.4 Device Functional Modes
8.4.1 Configuration Select MODE_SEL[1:0]
The DS90UH948-Q1 is capable of operating in either in 1-lane or 2-lane mode for FPD-Link III. By default, the
FPD-Link III receiver automatically configures the input based on 1- or 2-lane mode operation. Programming
register 0x34 [4:3] settings will override the automatic detection. For each FPD-Link III pair, the serial datastream
is composed of a 35-bit symbol.
The DS90UH948-Q1 recovers the FPD-Link III serial datastream(s) and produces video data driven to the
OpenLDI (LVDS) interface. OpenLDI Single Link and Dual Link are supported with color depths of 18 bits per
pixel or 24 bits per pixel. There are 8 differential data pairs (D0 through D7) and two clock pairs (CLK1 and
CLK2) on the OpenLDI interface. The number of data lines may vary, depending on the pixel formats supported.
For Single Link output the pixel clock is limited to 96 MHz. In the case of Dual Link, the pixel clock is limited to
170 MHz (or 85 MHz per LVDS port). When in a Dual Link configuration, LVDS channels D0 to D3 carry ODD
pixel data, and LVDS channels D4 to D7 carry EVEN pixel data.
The device can be configured in following modes:
• 1-lane FPD-Link III Input, Single Link OpenLDI Output
• 1-lane FPD-Link III Input, Dual Link OpenLDI Output
• 2-lane FPD-Link III Input, Dual Link OpenLDI Output
• 2-lane FPD-Link III Input, Single Link OpenLDI Output
• 2-lane FPD-Link III Input, Single Link OpenLDI Output (Replicate)
8.4.1.1 1-lane FPD-Link III Input, Single Link OpenLDI Output
In this configuration the PCLK rate embedded within the 1-lane FPD-Link III frame can range from 25 MHz to 96
MHz, resulting in a link rate of 875 Mbps (35 bit * 25 MHz) to 3.36 Gbps (35 bit * 96 MHz). Each LVDS data lane
will operate at a speed of 7 bits per LVDS clock cycle; resulting in a serial line rate of 175 Mbps to 672 Mbps.
CLK1 will operate at the same rate as PCLK with a duty cycle ratio of 57:43.
8.4.1.2 1-lane FPD-Link III Input, Dual Link OpenLDI Output
The input RGB data is split into odd and even pixels starting with the ODD (first) pixel outputs D0 to D3 and then
the EVEN (second) pixel outputs D4 to D7. The splitting of the data signals starts with DE (data enable)
transitioning from logic LOW to HIGH indicating active data.
In this configuration the PCLK rate embedded within the 1-lane FPD-Link III frame can range from 50 MHz to 96
MHz, resulting in a link rate of 1.75 Gbps (35 bit * 50 MHz) to 3.36 Gbps (35 bit * 96 MHz). Each LVDS data
lane will operate at a speed of 7 bits per 2 LVDS clock cycles, resulting in a serial line rate of 175 Mbps to 336
Mbps. CLK1 and CLK2 will operate at half the rate as PCLK with a duty cycle ratio of 57:43.
8.4.1.3 2-lane FPD-Link III Input, Dual Link OpenLDI Output
The input RGB data is split into odd and even pixels starting with the ODD (first) pixel outputs D0 to D3 and then
the EVEN (second) pixel outputs D4 to D7. The splitting of the data signals starts with DE (data enable)
transitioning from logic LOW to HIGH indicating active data.
In this configuration the PCLK rate embedded within 2-lane FPD-Link III frame can range from 50 MHz to 170
MHz, resulting in a link rate of 875 Mbps (35 bit * 25 MHz) to 2.975 Gbps (35 bit * 85 MHz). Each LVDS data
lane will operate at a speed of 7 bits per 2 LVDS clock cycles, resulting in a serial line rate of 175 Mbps to 595
Mbps. CLK1 and CLK2 will operate at half the rate as PCLK with a duty cycle ratio of 57:43.
8.4.1.4 2-lane FPD-Link III Input, Single Link OpenLDI Output
In this configuration the PCLK rate embedded within 2-lane FPD-Link III frame can range from 50 MHz to 170
MHz, resulting in a link rate of 875 Mbps (35 bit * 25 MHz) to 2.975 Gbps (35 bit * 85 MHz). Each LVDS data
lane will operate at a speed of 7 bits per LVDS clock cycle; resulting in a serial line rate of 350 Mbps to 1190
Mbps. CLK1 will operate at the twice the rate as PCLK with a duty cycle ratio of 57:43.
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