DS90UH948-Q1 Datasheet, PDF (30/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
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8.3.13.1 I2S Transport Modes
By default, packetized audio is received during video blanking periods in dedicated Data Island Transport frames.
The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio
configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.
In frame transport, only I2S_DA is received to the Deserializer. Surround Sound Mode, which transmits all four
I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode is only available
when connected to a DS90UH927Q, DS90UH949-Q1, DS90UH947-Q1, or DS90UH929-Q1 serializer. If
connected to a DS90UH925Q serializer, only I2S_DA and I2S_DB may be received.
8.3.13.2 I2S Repeater
I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via Data
Island Transport on the FPD-Link interface during the video blanking periods. If frame transport is desired, then
the I2S pins should be connected from the deserializer to all serializers. Activating surround sound at the top-
level serializer automatically configures downstream serializers and deserializers for surround sound transport
utilizing Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode
must be explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 11).
A DS90UH948-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input
pins in lieu of Data Island frames. See the Repeater Connection Diagram (Figure 27 ) and the I2C Control
Registers (Table 11) for additional details.
8.3.13.3 I2S Jitter Cleaning
This device features a standalone PLL to clean the I2S data jitter, supporting high-end car audio systems. If
I2S_CLK frequency is less than 1MHz, this feature must be disabled through register 0x2B[7]. See Table 11.
8.3.13.4 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports x1, x2, or x4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 7 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 11. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
Sample Rate
(kHz)
32
44.1
48
96
192
Table 7. Audio Interface Frequencies
I2S Data Word Size (bits) I2S_CLK (MHz)
1.024
1.4112
16
1.536
3.072
6.144
MCLK Output (MHz)
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
I2S_CLK x1
I2S_CLK x2
I2S_CLK x4
Register 0x3A[6:4]
000
001
010
000
001
010
000
001
010
001
010
011
010
011
100
30
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