DS90UH948-Q1 Datasheet, PDF (74/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90UH948-Q1 is a FPD-Link III Deserializer which, in conjunction with the DS90UH949/947-Q1
Serializers, converts 1-lane or 2-lane FPD-Link III streams into a FPD-Link (OpenLDI) interface. The Deserializer
is capable of operating over cost-effective 50Ω single-ended coaxial or 100Ω differential shielded twisted-pair
(STP) cables. It recovers the data from two FPD-Link III serial streams and translates it into dual pixel FPD-Link
(data lanes + clock) supporting video resolutions up to WUXGA and 1080p60 with 24-bit color depth. This
provides a bridge between HDMI enabled sources such as GPUs to connect to existing LVDS displays or
Application Processors.
9.2 Typical Applications
Bypass capacitors should be placed near the power supply pins. At a minimum, four (4) 10µF capacitors should
be used for local device bypassing. Ferrite beads are placed on the two sets of supply pins (VDD33 and VDDIO )
for effective noise suppression. The interface to the graphics source is LVDS. The VDDIO pins may be
connected to 3.3V or 1.8V. A capacitor and resistor are placed on the PDB pin to delay the enabling of the
device until power is stable. See Figure 46 for a typical STP connection diagram and Figure 47 for a typical coax
connection diagram.
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