DS90UH948-Q1 Datasheet, PDF (45/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Image Enhancement Features (continued)
8.5.3 Enabling White Balance
The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be
followed by the user.
To initialize white balance after power-on:
1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third
BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance. By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This
option may only be used after enabling the white balance reload feature via the associated serial control bus
register. In this mode the LUTs may be reloaded by the master controller via I2C. This provides the user with the
flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The
host controller loads the updated LUT values via the serial bus interface. There is no need to disable the white
balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be
seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When
reloading, partial LUT updates may be made. Note, the LUT cannot be read.
8-bit in / 8 bit out
Gray level Data Out
Entry
(8-bits)
0 00000000b
1 00000001b
2 00000011b
3 00000011b
4 00000110b
5 00000110b
6 00000111b
7 00000111b
8 00001000b
9 00001010b
10 00001001b
11 00001011b
6-bit in / 6 bit out
Gray level Data Out
Entry
(8-bits)
0 00000000b
1 N/A
2 N/A
3 N/A
4 00000100b
5 N/A
6 N/A
7 N/A
8 00001000b
9 N/A
10 N/A
11 N/A
6-bit in / 8 bit out
Gray level Data Out
Entry
(8-bits)
0 00000001b
1 N/A
2 N/A
3 N/A
4 00000110b
5 N/A
6 N/A
7 N/A
8 00001011b
9 N/A
10 N/A
11 N/A
248 11111010b
249 11111010b
250 11111011b
251 11111011b
252 11111110b
253 11111101b
254 11111101b
255 11111111b
248 11111000b
249 N/A
250 N/A
251 N/A
252 11111100b
253 N/A
254 N/A
255 N/A
248 11111010b
249 N/A
250 N/A
251 N/A
252 11111111b
253 N/A
254 N/A
255 N/A
Figure 40. White Balance LUT Configuration
8.5.4 Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits
per sub-pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use
lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a
lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by
controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off
pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and
also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full
(16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to
apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of
each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is
enabled via serial control bus register. Two FRC functional blocks are available, and may be independently
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