DS90UH948-Q1 Datasheet, PDF (65/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(hex)
0x37
Register
Name
MODE_SEL
Bit(s) Function
7
MODE_SEL1
DONE
Type
RW
6:4 MODE_SEL1
RW
3
MODE_SEL0
RW
DONE
2:0 MODE_SEL0
RW
0x3A I2S_DIVSEL 7
reg_ov_mdiv
RW
6:4 reg_mdiv
RW
3
RESERVED
R
2
reg_ov_mselect RW
1:0 reg_mselect
RW
Default
Description
Value (hex)
0
MODE_SEL1 Done:
0: indicates the MODE_SEL1 decode has not been latched into
the MODE_SEL1 status bits.
1: indicates the MODE_SEL1 decode has completed and
latched into the MODE_SEL1 status bits.
0
MODE_SEL1 Decode
3-bit decode from MODE_SEL1 pin, see MODE_SEL1 table
first column "#" for mode selection:
000: CSI0 / 5 Mbps / STP (#1 on MODE_SEL1)
001: CSI0 / 5 Mbps / coax (#2 on MODE_SEL1)
010: CSI0 / 20 Mbps / STP (#3 on MODE_SEL1)
011: CSI0 / 20 Mbps / coax (#4 on MODE_SEL1)
100: CSI1 / 5 Mbps / STP (#5 on MODE_SEL1)
101: CSI1 / 5 Mbps / coax (#6 on MODE_SEL1)
110: CSI1 / 20 Mbps / STP (#7 on MODE_SEL1)
111: CSI1 / 20 Mbps / coax (#8 on MODE_SEL1)
Note: 0x37[6] is the MSB; 0x37[4] is the LSB
0
MODE_SEL0 Done:
0: indicates the MODE_SEL0 decode has not been latched into
the MODE_SEL0 status bits.
1: indicates the MODE_SEL0 decode has completed and
latched into the MODE_SEL0 status bits.
0
MODE_SEL0 Decode
3-bit decode from MODE_SEL0 pin, see MODE_SEL0 table
first column "#" for mode selection:
000: 4 data lanes, 1 CSI port active
..........Active CSI port determined by MODE_SEL1 CSI_SEL bit.
.......... (#1 on MODE_SEL0)
001: 4 data lanes, both CSI ports active
..........overrides MODE_SEL1. (#2 on MODE_SEL0)
010: 2 data lanes, 1 CSI port active
..........Active CSI port determined by MODE_SEL1 CSI_SEL bit.
.......... (#3 on MODE_SEL0)
011: 2 data lanes, both CSI port active
..........overrides MODE_SEL1. (#4 on MODE_SEL0)
100: RESERVED (#5 on MODE_SEL0)
101: RESERVED (#6 on MODE_SEL0)
110: RESERVED (#7 on MODE_SEL0)
111: RESERVED (#8 on MODE_SEL0)
Note: 0x37[2] is the MSB; 0x37[0] is the LSB
0x0
0: No override for MCLK divider
1: Override divider select for MCLK
0x0
Divide ratio select for VCO output (32*REF/M)
000: Divide by 32 (=REF/M)
001: Divide by 16 (=2*REF/M)
010: Divide by 8 (=4*REF/M)
011: Divide by 4 (=8*REF/M)
100: Reserved
101: Divide by 2 (=16*REF/M)
110: Reserved
111: Divide by 1 (32*REF/M)
0x0
0x0
0: Divide ratio of reference clock VCO selected by PLL-SM
1: Override divide ratio of clock to VCO
0x0
Divide ratio select for VCO input (M)
00: Divide by 1
01: Divide by 2
10: Divide by 4
11: Divide by 8
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