DS90UH948-Q1 Datasheet, PDF (70/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
www.ti.com
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(hex)
0x6E
0x6F
0x80
0x81
0x82
0x83
0x84
0x90
0x91
0x92
0x93
0x94
0xC0
Register
Name
GPI Pin
Status 1
GPI Pin
Status 2
RX_BKSV0
RX_BKSV1
RX_BKSV2
RX_BKSV3
RX_BKSV4
TX_KSV0
TX_KSV1
TX_KSV2
TX_KSV3
TX_KSV4
HDCP_DBG
Bit(s)
7
6
5
4
3
2
1
0
7:1
0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7
6
Function
GPI7 Pin Status
GPI6 Pin Status
GPI5 Pin Status
RESERVED
GPI3 Pin Status
GPI2 Pin Status
GPI1 Pin Status
GPI0 Pin Status
RESERVED
GPI8 Pin Status
BKSV0
BKSV1
BKSV2
BKSV3
BKSV4
TX_KSV0
TX_KSV1
TX_KSV2
TX_KSV3
TX_KSV4
RESERVED
HDCP_I2C_TO_
DIS
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
5:4 RESERVED
R
3
RGB_CHKSUM_ R
EN
2
FAST_LV
R
1
TMR_SPEEDUP R
0
HDCP_I2C_
R
FAST
Default
Description
Value (hex)
0
GPI7/I2S_WC pin status
0
GPI6/I2S_DA pin status
0
GPI5/I2S_DB pin status
0
Reserved for future use
0
GPI3 / I2S_DD pin status
0
GPI2 / I2S_DC pin status
0
GPI1 pin status
0
GPI0 pin status
0
Reserved for future use
0
GPI8/I2S_CLK pin status
0
BKSV0: Value of byte0 of the Receiver KSV.
0
BKSV1: Value of byte1 of the Receiver KSV.
0
BKSV2: Value of byte2 of the Receiver KSV.
0
BKSV3: Value of byte3 of the Receiver KSV.
0
BKSV4: Value of byte4 of the Receiver KSV.
0
TX_KSV0: Value of byte0 of the Transmitter KSV.
0
TX_KSV1: Value of byte1 of the Transmitter KSV.
0
TX_KSV2: Value of byte2 of the Transmitter KSV.
0
TX_KSV3: Value of byte3 of the Transmitter KSV.
0
TX_KSV4: Value of byte4 of the Transmitter KSV.
0
Reserved
0
HDCP I2C Timeout Disable:
Setting this bit to a 1 will disable the bus timeout function in the
HDCP I2C master. When enabled, the bus timeout function
allows the I2C master to assume the bus is free if no signaling
occurs for more than 1 second. Set via the HDCP_DBG register
in the HDCP Transmitter.
0
Reserved
0
Enable RGB video line checksum:
Enables sending of ones-complement checksum for each 8-bit
RGB data channel following end of each video data line. Set via
the HDCP_DBG register in the HDCP Transmitter.
0
Fast Link Verification:
HDCP periodically verifies that the HDCP Receiver is correctly
synchronized. Setting this bit will increase the rate at which
synchronization is verified. When set to a 1, Pj is computed
every 2 frames and Ri is computed every 16 frames. When set
to a 0, Pj is computed every 16 frames and Ri is computed
every 128 frames. Set via the HDCP_DBG register in the HDCP
Transmitter.
0
Timer Speedup:
Speed up HDCP authentication timers. Set via the HDCP_DBG
register in the HDCP Transmitter.
0
HDCP I2C Fast mode Enable:
Setting this bit to a 1 will enable the HDCP I2C Master in the
HDCP Receiver to operation with Fast mode timing. If set to a
0, the I2C Master will operation with Standard mode timing. Set
via the HDCP_DBG register in the HDCP Transmitter.
70
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