DS90UH948-Q1 Datasheet, PDF (5/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
D6-
26
O, LVDS Channel 6 Differential Output
D6+
25
This pair requires an external 100 Ω termination for LVDS
D7-
22
O, LVDS Channel 7 Differential Output
D7+
21
This pair requires an external 100 Ω termination for LVDS
FPD-LINK III INTERFACE - Layout note: for unused FPD-LinkIII inputs, float those pins (do not connect to an external pullup or
pulldown)
RIN0-
54
I/O, CML FPD-Link III Inverting Input/Output
The output must be AC-coupled with a 33 nF capacitor.
RIN0+
53
I/O, CML FPD-Link III True Input/Output
The output must be AC-coupled with a 33 nF capacitor.
RIN1-
59
I/O, CML FPD-Link III Inverting Input/Output
The output must be AC-coupled with a 33 nF capacitor.
RIN1+
58
I/O, CML FPD-Link III True Input/Output
The output must be AC-coupled with a 33 nF capacitor.
CMF
55
I/O, CML Common Mode Filter. Connect 0.1 µF capacitor to GND
I2C PINS
I2C_SDA
46
I/O, Open- I2C Data Input / Output interface
Drain
Open drain. Must have an external pull-up resistor to VDDIO DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
I2C_SCL
45
I/O, Open- I2C Clock Input / Output Interface
Drain
Open drain. Must have an external pull-up resistor to VDDIO DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
IDx
47
I,
Analog input. I2C Serial Control Bus Device ID Address. Table 10
Analog
Configuration
Pin
SPI PINS (Pin function programmed through register) - Layout note: for unused SPI pins, tie to an external pulldown
MOSI
(D_GPIO0)
19
Multi-function Master Out, Slave In.
pin
(Pin is shared with D_GPIO0)
I/O, LVCMOS
w/ weak
internal PD
MISO
(D_GPIO1)
18
Multi-function Master In, Slave Out.
pin
(Pin is shared with D_GPIO1)
I/O, LVCMOS
w/ weak
internal PD
SPLK
(D_GPIO2)
17
Multi-function Serial clock.
pin
(Pin is shared with D_GPIO2)
I/O, LVCMOS
w/ weak
internal PD
SS
(D_GPIO3)
16
Multi-function Slave select.
pin
(Pin is shared with D_GPIO3)
I/O, LVCMOS
w/ weak
internal PD
CONTROL PINS
MODE_SEL0
61
I,
Analog input. Mode Select 0. Connect to external pull-up to VDD33 and pull-down to
Analog
GND to create a voltage divider. See Configuration Select (MODE_SEL0) Table 8
Configuration
Pin
MODE_SEL1
50
I,
Analog input. Mode Select 1. Connect to external pull-up to VDD33 and pull-down to
Analog
GND to create a voltage divider. See Configuration Select (MODE_SEL1) Table 9
Configuration
Pin
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