DS90UH948-Q1 Datasheet, PDF (63/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
ADD
(hex)
0x2A
Register
Name
White
Balance
Control
0x2B I2S Control
0x2E PCLK Test
Mode
Table 11. Serial Control Bus Registers (continued)
Bit(s) Function
7:6 Page Setting
Type
RW
5
White Balance RW
Enable
4
LUT Reload
RW
Enable
3:0 RESERVED
RW
7:4 RESERVED
RW
3
I2S FIFO
R
OVERRUN
STATUS
2
I2S FIFO
R
UNDERRUN
STATUS
1
I2S FIFO
RW
ERROR RESET
0
I2S DATA
RW
FALLING EDGE
7
EXTERNAL
RW
PCLK
6:0 RESERVED
RW
Default
Description
Value (hex)
0
Page setting
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
0
0: White Balance Disable
1: White Balance Enable
0
0: Reload Disable
1: Reload Enable
0
Reserved
0
Reserved
0
I2S FIFO Overrun Status
0
I2S FIFO Underrun Status
0
I2S Fifo Error Reset
1: Clears FIFO Error
0
I2S Clock Edge Select
1: I2S Data is strobed on the Rising Clock Edge.
0: I2S Data is strobed on the Falling Clock Edge.
0
Select pixel clock from BISTC input
0
Reserved
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