DS90UH948-Q1 Datasheet, PDF (23/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Feature Description (continued)
Setting the PORT1_SEL and PORT0_SEL bit will allow a read of the register for the selected port. If both bits are
set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing simultaneous
writes to both ports if both select bits are set.
8.3.4 Oscillator Output
The deserializer provides an optional CLK[2:1]± output when the input clock (serial stream) has been lost. This is
based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable). See
Table 11.
8.3.5 Clock and Output Status
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is tri-state or LOW
(depending on the value of the OUTPUT ENABLE setting). After the deserializer completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the LVCMOS and LVDS outputs. The State of the outputs is based on the OUTPUT
ENABLE and OUTPUT SLEEP STATE SELECT register settings. See register 0x02 in Table 11.
Serial
Input
X
X
X
Static
Static
Active
Active
PDB
L
H
H
H
H
H
H
Inputs
OUTPUT ENABLE
Reg 0x02 [7]
X
L
L
H
H
H
H
Table 2. Output State Table
OUTPUT SLEEP
STATE SELECT
Reg 0x02 [4]
X
L
H
L
H
L
H
LOCK
Z
L
L or H
L
L
L
H
Outputs
PASS
Data
GPIO / D_GPIO
I2S
Z
Z
L
L
Z
Z
L
L
Previous Status
L
Valid
L
L
Valid
D[7:0] /
CLK[2:1]
Z
L
Z
L/OSC (Register
EN)
L
L
Valid
8.3.6 LVCMOS VDDIO Option
The 1.8V or 3.3V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with
external system interface signals.
NOTE
When configuring the VDDIO power supplies, all the single-ended data and control input
pins for device need to scale together with the same operating VDDIO levels.
8.3.7 Power Down (PDB)
The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the host or through the VDDIO, where VDDIO = 3.0V to 3.6 V or VDD33. To save power, disable the link when
the display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33
and VDDIO have reached final levels; no external components are required. In the case of driven by the VDDIO
= 3.0 V to 3.6 V or VDD33 directly, a 10kΩ resistor to the VDDIO = 3.0 V to 3.6 V or VDD33, and a >10 µF
capacitor to the GND are required (see Figure 46 Typical Connection Diagram).
8.3.8 Interrupt Pin — Functional Description and Usage (INTB_IN)
The INTB_IN pin is an active low interrupt input pin. This interrupt signal, when configured, will propagate to the
paired serializer. Consult the appropriate Serializer datasheet for details of how to configure this interrupt
functionality.
1. On the Serializer, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. Deserializer INTB_IN (pin 4) is set LOW by some downstream device.
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