DS90UH948-Q1 Datasheet, PDF (28/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
DESERIALIZER
SS
SPLK
MOSI
D0
D1
D2
D3
DN
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SS
SERIALIZER
SPLK
MOSI
D0
D1
D2
D3
DN
Figure 21. Reverse Channel SPI Write
For Reverse Channel SPI reads, the SPI master must wait for a round-trip response before generating the
sampling edge of the SPI clock. This is similar to operation in Forward channel mode. Note that at most one
data/clock sample will be sent per back channel frame.
DESERIALIZER
SS
SPLK
MOSI
D0
D1
MISO
RD0
RD1
SS
SERIALIZER
SPLK
D0
MOSI
MISO
RD0
RD1
Figure 22. Reverse Channel SPI Read
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