DS90UH948-Q1 Datasheet, PDF (22/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
8.2 Functional Block Diagram
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RIN0+
RIN0-
1st Link
Open LDI LVDS
Outputs
RIN1+
RIN1-
CMLOUTP
CMLOUTN
PDB
LOCK
PASS
MODE_SEL0
MODE_SEL1
4
D_GPIOx / SPI /
8
I2S / GPIO /
Timing
and
Control
Clock
Gen
I2C
Controller
2nd Link
Open LDI LVDS
Outputs
CLOCK
Open LDI LVDS
Outputs
I2C_SDA
I2C_SCL
IDx
8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, HDCP,
I2C, GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 18 illustrates the serial stream per
clock cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 18. FPD-Link III Serial Stream
The DS90UH948-Q1 supports clocks in the range of 25 MHz to 96 MHz over a 1-lane, or 50MHz to 170MHz
over 2-lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) or 2.975 Gbps
maximum per lane (875 Mbps minimum) respectively.
8.3.2 Low Speed Back Channel Data Transfer
The Low-Speed Backward Channel provides bidirectional communication between the display and host
processor. The information is carried from the deserializer to the serializer as serial frames. The back channel
control data is transferred over both serial links along with the high-speed forward data, DC balance coding and
embedded clock information. This architecture provides a backward path across the serial link together with a
high speed forward channel. The back channel contains the I2C, HDCP, CRC and 4 bits of standard GPIO
information with 5 or 20 Mbps line rate (configured by MODE_SEL1).
8.3.3 FPD-Link III Port Register Access
Since the DS90UH948-Q1 contains two ports, some registers need to be duplicated to allow control and
monitoring of the two ports. To facilitate this, PORT1_SEL and PORT0_SEL bits (0x34[1:0]) register controls
access to the two sets of registers. Registers that are shared between ports (not duplicated) will be available
independent of the settings in the PORT_SEL register.
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