DS90UH948-Q1 Datasheet, PDF (64/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
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Register Maps (continued)
ADD
(hex)
0x34
Register
Name
DUAL_RX_
CTL
0x35 AEQ TEST
Table 11. Serial Control Bus Registers (continued)
Bit(s) Function
7
RESERVED
6
RX_LOCK_
MODE
Type
R
RW
5
RAW_2ND_BC RW
4:3 FPD3 INPUT
RW
MODE
2
RESERVED
RW
1
PORT1_SEL
RW
0
PORT0_SEL
RW
7
RESERVED
RW
6
AEQ_RESTART RW
5
OVERRIDE_AEQ RW
_
FLOOR
4
SET_AEQ_
RW
FLOOR
3:0 RESERVED
RW
Default
Description
Value (hex)
0
Reserved
0
RX Lock Mode:
Determines operating conditions for indication of RX_LOCK and
generation of video data.
0 : RX_LOCK asserted only when receiving active video
(Forward channel VIDEO_DISABLED bit is 0)
1 : RX_LOCK asserted when device is linked to a Serializer
even if active video is not being sent. This allows indication of
valid link where Bidirectional Control Channel is enabled, but
Deserializer is not receiving Audio/Video data.
0
Enable Raw Secondary Back channel
If this bit is set to a 1, the secondary back channel will operate
in a raw mode, passing D_GPIO0 from the Deserializer to the
Serializer, without any oversampling or filtering.
0
FPD-Link III Input Mode
Determines operating mode of FPD-Link III Receive interface
00: Auto-detect based on received data
01: Forced Mode: 2-lane
10: Forced Mode: 1-lane, primary input
11: Forced Mode: 1-lane, secondary input
0
Reserved
0
Selects Port 1 for Register Access from primary I2C Address
For writes, port1 registers and shared registers will both be
written.
For reads, port1 registers and shared registers will be read.
This bit must be cleared to read port0 registers.
1
Selects Port 0 for Register Access from primary I2C Address
For writes, port0 registers and shared registers will both be
written.
For reads, port0 registers and shared registers will both be
read.
Note that if PORT1_SEL is also set, then port1 registers will be
read.
AEQ Test register
If PORT1_SEL is set, this register sets port1 AEQ controls
0
Reserved
0
Set high to restart AEQ adaptation from initial value. Method is
write HIGH then write LOW - not self clearing. Adaption will be
restarted on both ports.
0
Enable operation of SET_AEQ_FLOOR
0
AEQ adaptation starts from a pre-set floor value rather than
from zero - recommended for long cable situations
0x0
Reserved
64
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