DS90UH948-Q1 Datasheet, PDF (20/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Power Sequence (continued)
Symbol
t₄
t₁
t₂
t₅
Table 1. Power-Up Sequencing Constraints (continued)
Description
VDD12 rise time
VDDIO delay time
VDD12 delay time
Startup time
Test Conditions
Min
Typ
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
V_IL of rising edge (VDDIO ) to V_IL of
rising edge (VDD_N)
The power supplies may be ramped
simultaneously. If sequenced, VDD33
>0
should be first, either by itself or with
VDDIO (1.8V or 3.3V) or VDD12, with the
other rail(s) following in any order.
The part is powered up after the startup
time has elapsed from the moment PDB
goes HIGH. Local I2C is available to
read/write 948/940 registers after this
time.
7.12 Typical Characteristics
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Max
Units
<1.5
ms
ms
<1
ms
Time (50 ps/DIV)
Figure 16. Deserializer Eye Diagram with 3.36 Gbps FPD-
Link III Rate
Time (2.5 ns/DIV)
Figure 17. OpenLDI Output with 96 MHz Clock
20
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