DS90UH948-Q1 Datasheet, PDF (13/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
7.7 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
GPIO BIT RATE
R_b,FC
Forward Channel Bit Rate
Single OLDI Output. OLDI Clock GPIO[3:0]
= 25 - 96MHz
Dual OLDI Output. OLDI Clock =
25 - 85MHz
R_b,BC
R_b,BC
Back Channel Bit Rate
Back Channel Bit Rate
t_GPIO,FC
GPIO Pulse Width, Forward
Channel
High Speed (2-lane Mode), 1
D_GPIO active.
See Table 4.
High Speed (2-lane Mode), 2
D_GPIO's active.
See Table 4.
High Speed (2-lane Mode), 4
D_GPIO's active.
See Table 4.
Normal mode. See Table 4.
D_GPIO[3:0]
GPIO[3:0]
t_GPIO,BC
RESET
GPIO Pulse Width, Back Channel
t_LRST
PDB Reset Low Pulse
LOOP-THROUGH MONITOR OUTPUT
E_W
Differential Output Eye Opening
Width
E_H
Differential Output Eye Height
FPD-LINK III CML INPUT
RL = 100Ω, Jitter frequency
>OLDI Clock / 40
See Figure 2.
t_DDLT
Lock Time
See Figure 6.
I2S TRANSMITTER
t_J,I2S
t_I2S
Clock Output Jitter
I2S Clock Period⁽²⁾
See Figure 14.
GPIO[3:0]
PDB
CMLOUTP,
CMLOUTN
RIN0+,
RIN0-,
RIN1+,
RIN1-
I2S_CLK
t_HC,I2S
t_LC,I2S
t_SR,I2S
t_HR,I2S
I2S Clock High Time⁽²⁾
I2S Clock Low Time⁽²⁾
I2S Set-up Time
I2S Hold Time
See Figure 14.
See Figure 14.
See Figure 14.
See Figure 14.
I2S_DA,
I2S_DB,
I2S_DC,
I2S_DD
MIN
>2 /
OLDI
Clock
20
2
TYP
0.25 *
OLDI
Clock
0.25 *
OLDI
Clock
133
2.0
1.33
800
133
0.4
>300
5
2
>2 /
OLDI
Clock
or >77
0.48
0.48
0.4
0.4
MAX UNIT
Mbps
Mbps
kbps
Mbps
Mbps
kbps
kbps
s
μs
ms
UI
mV
10⁽¹⁾ ms
ns
ns
t_I2S
t_I2S
t_I2S
t_I2S
(1) This parameter is specified by characterization and is not tested in production.
(2) I2S specifications for t_LC,I2S and t_HC,I2S pulses must each be greater than 1 OLDI clock period to ensure sampling and supersedes the
0.35*t_I2S requirement. t_LC,I2S and t_HC,I2S must be longer than the greater of either 0.35*t_I2S or 2 * OLDI Clock .
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