DS90UH948-Q1 Datasheet, PDF (77/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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Graphics
Processor
FPD-Link
(Open LDI)
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
D4+/-
D5+/-
D6+/-
D7+/-
DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
VDDIO
1.8V
1.8V 1.1V
DOUT0+
DOUT0-
DOUT1+
DOUT1-
DS90UH947-Q1
Serializer
FPD-Link III
2 lanes
1.2V 3.3V
VDDIO
1.8V or 3.3V
RIN0+
RIN0-
RIN1+
RIN1-
DS90UH948-Q1
Deserializer
I2C
I2C
IDx
IDx
HS_GPIO
(SPI) HS_GPIO
(SPI)
Figure 48. Typical Display System Diagram
FPD-Link
(Open LDI)
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
CLK2+/-
D4+/-
D5+/-
D6+/-
D7+/-
LVDS
Display
1080p60
or Graphic
Processor
9.2.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 12. Design Parameters
Design Parameter
VDDIO
VDD12
VDD33
AC Coupling Capacitor for RIN0± and RIN1±
Example Value
1.8V or 3.3V
1.2V
3.3V
33 nF
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 49. For applications utilizing single-ended 50 Ω coaxial cable, the unused data pins (RIN0-, RIN1-) should
utilize a 15 nF capacitor and should be terminated with a 50 Ω resistor.
SER
D_OUT+
D_OUT-
R_IN+
R_IN-
DES
Figure 49. AC-Coupled Connection (STP)
SER
D_OUT+
R_IN+
DES
D_OUT-
50Q
50Q
R_IN-
Figure 50. AC-Coupled Connection (Coaxial)
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require 33 nF
AC coupling capacitors to the line.
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