DS90UH948-Q1 Datasheet, PDF (7/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Pin Functions (continued)
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
GPIO7_REG
(I2S_WC)
14
Multi-function General Purpose Input/Output 7
pin
I2C register control only.
I/O, LVCMOS default state: logic LOW
(Pin is shared with I2S_WC)
GPIO8_REG
(I2S_CLK)
13
Multi-function General Purpose Input/Output 8
pin
I2C register control only.
I/O, LVCMOS default state: logic LOW
(Pin is shared with I2S_CLK)
SLAVE MODE LOCAL I2S CHANNEL PINS (Pin function programmed through register) - Layout note: for unused I2S outputs, tie
to an external pulldown
I2S_WC
(GPIO7_REG)
14
Multi-function Slave Mode I2S Word Clock Output.
pin
(Pin is shared with GPIO7_REG)
O, LVCMOS
I2S_CLK
(GPIO8_REG)
13
Multi-function Slave Mode I2S Clock Output.
pin
(Pin is shared with GPIO8_REG)
O, LVCMOS
I2S_DA
(GPIO6_REG)
12
Multi-function Slave Mode I2S Data Output.
pin
(Pin is shared with GPIO6_REG)
O, LVCMOS
I2S_DB
(GPIO5_REG)
11
Multi-function Slave Mode I2S Data Output.
pin
(Pin is shared with GPIO5_REG)
O, LVCMOS
I2S_DC
(GPIO2_REG)
10
Multi-function Slave Mode I2S Data Output.
pin
(Pin is shared with GPIO2)
O, LVCMOS
I2S_DD
(GPIO3_REG)
9
Multi-function Slave Mode I2S Data Output.
pin
(Pin is shared with GPIO3)
O, LVCMOS
MASTER MODE LOCAL I2S CHANNEL PINS (Pin function programmed through register) - Layout note: for unused GPIO(s), tie to
an external pulldown
SWC
(GPIO1)
8
Multi-function Master Mode I2S Word Clock Output.
pin
(Pin is shared with GPIO1)
O, LVCMOS
SDOUT
(GPIO0)
7
Multi-function Master Mode I2S Data Output.
pin
(Pin is shared with GPIO0)
O, LVCMOS
MCLK
(GPIO9)
15
Multi-function Master Mode I2S System Clock Output.
pin
(Pin is shared with GPIO9)
O, LVCMOS
STATUS PINS - Layout note: add a test point (TP) on these pins
LOCK
1
O, LVCMOS Lock Status Output
LOCK = 1: PLL acquired lock to the reference clock input
LOCK = 0: PLL is unlocked
PASS
7
POWER & GROUND ⁽¹⁾
O, LVCMOS
BIST mode status output pin (BISTEN = 1)
PASS = 1: No error detected
PASS = 0: Error detected
VDD33_A,
VDD33_B
56
Power
3.3V (±10%) supply. Power to on-chip regulator. Requires 10 µF, 1 µF, 0.1 µF, and
31
0.01 µF capacitors to GND
VDDIO
3
Power
LVCMOS I/O power supply, 1.8V (±5%) OR 3.3V (±10%). Requires 10 µF, 1 µF, 0.1 µF,
and 0.01 µF capacitors to GND
(1) The VDD (VDD12, VDD33, and VDDIO) supply ramp should be faster than 1.5ms with a monotonic rise
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