DS90UH948-Q1 Datasheet, PDF (51/91 Pages) Texas Instruments – FPD-Link III to OpenLDI Deserializer

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DS90UH948-Q1
SNLS473A – OCTOBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
Table 11. Serial Control Bus Registers (continued)
ADD
(hex)
0x03
Register
Name
Bit(s)
General
7
Configuration
1
6
Function
RESERVED
BC CRC
GENERATOR
ENABLE
5
FAILSAFE LOW
Type
RW
RW
RW
4
FILTER ENABLE RW
3
I2C PASS-
RW
THROUGH
2
AUTO ACK
RW
1
DE GATE RGB RW
0
RESERVED
RW
0x04 BCC
7:1 BCC
RW
Watchdog
WATCHDOG
Control
TIMER
0
0x05 I2C Control 1 7
BCC
RW
WATCHDOG
TIMER DISABLE
I2C PASS
RW
THROUGH ALL
6:4 I2C SDA HOLD RW
3:0 I2C FILTER
RW
DEPTH
Default
Description
Value (hex)
1
Reserved
1
Back Channel CRC Generator Enable
0: Enable
1: Disable (Default)
1
Controls the pull direction for undriven LVCMOS inputs
1: Pull down
0: Pull up
1
HS,VS,DE two clock filter
When enabled, pulses less than two full PCLK cycles on the
DE, HS, and VS inputs will be rejected.
1: Filtering enable
0: Filtering disable
0
I2C Pass-Through to Serializer if decode matches
0: Pass-Through Disabled
1: Pass-Through Enabled
0
Automatically Acknowledge I2C writes independent of the
forward channel lock state
1: Enable
0: Disable
0
Gate RGB data with DE signal. RGB data is gated with DE in
order to allow packetized audio and block unencrypted data
when paired with a serializer that supports HDCP. When paired
with a serializer that does not support HDCP, RGB data is not
gated with DE by default. However, to enable packetized autio
this bit must be set.
1: Gate RGB data with DE (has no effect when paired with a
serializer that supports HDCP)
0: Pass RGB data independent of DE (has no effect when
paired with a serializer that does not support HDCP)
0
Reserved
0x7F
The watchdog timer allows termination of a control channel
transaction if it fails to complete within a programmed amount of
time. This field sets the Bidirectional Control Channel Watchdog
Timeout value in units of 2 milliseconds. This field should not be
set to 0.
0
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
0
I2C Pass-Through All Transactions
0: Disabled
1: Enabled
0x1
Internal SDA Hold Time
This field configures the amount of internal hold time provided
for the SDA input relative to the SCL input. Units are 50
nanoseconds.
0xE
I2C Glitch Filter Depth
This field configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5
nanoseconds.
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