CC2430 Datasheet, PDF (95/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
13.2.7 DMA registers
This section describes the SFR registers associated with the DMA Controller
DMAARM (0xD6) – DMA Channel Arm
Bit
Name
7
ABORT
6:5 -
4
DMAARM4
3
DMAARM3
2
DMAARM2
1
DMAARM1
0
DMAARM0
Reset
0
00
0
0
0
0
0
R/W Description
R0/W ^{DMA abort. This bit is used to stop ongoing DMA transfers.}
Writing a 1 to this bit will abort all channels which are
selected by setting the corresponding DMAARM bit to 1
0 : Normal operation
1 : Abort channels all selected channels
R/W ^{Not used}
R/W
DMA arm channel 4
This bit must be set in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes,
the bit is automatically cleared upon completion.
R/W
DMA arm channel 3
This bit must be set in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes,
the bit is automatically cleared upon completion.
R/W
DMA arm channel 2
This bit must be set in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes,
the bit is automatically cleared upon completion.
R/W
DMA arm channel 1
This bit must be set in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes,
the bit is automatically cleared upon completion.
R/W
DMA arm channel 0
This bit must be set in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes,
the bit is automatically cleared upon completion.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 95 of 232