CC2430 Datasheet, PDF (118/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
13.6 8-bit Timer 3 and Timer 4
Timer 3 and 4 are 8-bit timers which support
typical input capture and output compare
operations using two capture/compare
channels each. The timer allows general
purpose timer and waveform generation
functions.
Features of Timer 3/4 are as follows:
• Dual channel operation
• Rising, falling or any edge input compare
• Set, clear or toggle output compare
• Clock prescaler for divide by 1, 2, 4, 8, 16,
32, 64, 128
• Interrupt request generated on each
capture/compare and terminal count event
• DMA trigger function
13.6.1 8-bit Timer Counter
All timer functions are based on the main 8-bit
counter found in Timer 3/4. The counter
increments or decrements at each active clock
edge. The period of the active clock edges is
defined by the register bits CLKCON.TICKSPD
which is further divided by the prescaler value
set by TxCTL.DIV (where x refers to the
timer number, 3 or 4). The counter operates as
either a free-running counter, a down counter,
a modulo counter or as an up/down counter.
It is possible to read the 8-bit counter value
through the SFR TxCNT where x refers to the
timer number, 3 or 4.
The possibility to clear and halt the counter is
given with TxCTL control register settings. The
counter is started when a 1 is written to
TxCTL.START. If a 0 is written to
TxCTL.START the counter halts at its present
value.
13.6.2 Timer 3/4 Mode Control
In general the control register TxCTL is used
to control the timer operation.
13.6.2.1 Free-running Mode
In the free-running mode of operation the
counter starts from 0x00 and increments at
each active clock edge. When the counter
reaches 0xFF the counter is loaded with 0x00
and continues incrementing its value. When
the terminal count value 0xFF is reached (i.e.
an overflow occurs), the interrupt flag
TIMIF.TxOVFIF is set. If the corresponding
interrupt mask bit TxCTL.OVFIM is set, an
interrupt request is generated. The free-
running mode can be used to generate
independent time intervals and output signal
frequencies.
13.6.2.2 Down mode
In the down mode, after the timer has been
started, the counter is loaded with the contents
in TxCC. The counter then counts down to
0x00. The flag TIMIF.TxOVFIF is set when
0x00 is reached. If the corresponding interrupt
mask bit TxCTL.OVFIM is set, an interrupt
request is generated. The timer down mode
can generally be used in applications where an
event timeout interval is required.
13.6.2.3 Modulo Mode
When the timer operates in modulo mode the
8-bit counter starts at 0x00 and increments at
each active clock edge. When the counter
reaches the terminal count value held in
register TxCC the counter is reset to 0x00 and
continues to increment. The flag
TIMIF.TxOVFIF is set when on this event. If
the corresponding interrupt mask bit
TxCTL.OVFIM is set, an interrupt request is
generated. The modulo mode can be used for
applications where a period other than 0xFF is
required.
13.6.2.4 Up/down Mode
In the up/down timer mode, the counter
repeatedly starts from 0x00 and counts up until
the value held in TxCC is reached and then the
counter counts down until 0x00 is reached.
This timer mode is used when symmetrical
output pulses are required with a period other
than 0xFF, and therefore allows
implementation of centre-aligned PWM output
applications.
Clearing the counter by writing to TxCTL.CLR
will also reset the count direction to the count
up from 0x00 mode.
13.6.3 Channel Mode Control
The channel modes for each channel; 0 and 1,
are set by the control and status registers
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 118 of 232