CC2430 Datasheet, PDF (70/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
In addition to these common interrupt enables,
the bits within each port have interrupt enables
located in I/O port SFR registers. Each bit
within P1 has an individual interrupt enable. In
P0 the low-order nibble and the high-order
nibble have their individual interrupt enables.
For the P2_0 – P2_4 inputs there is a common
interrupt enable.
When an interrupt condition occurs on one of
the general purpose I/O pins, the
corresponding interrupt status flag in the P0-
P2 interrupt flag registers, P0IFG , P1IFG or
P2IFG will be set to 1. The interrupt status flag
is set regardless of whether the pin has its
interrupt enable set. When an interrupt is
serviced the interrupt status flag is cleared by
writing to a 0 to that flag.
Note that when clearing the PxIFG interrupt
status flags, only one active flag should be
cleared at a time. Failure to do this may result
in generation of false interrupt requests.
The I/O SFR registers used for interrupts are
described in section 13.1.9 on page 73. The
registers are summarized below:
• P1IEN : P1 interrupt enables
• PICTL : P0/P2 interrupt enables and P0-2
edge configuration
• P0IFG : P0 interrupt flags
• P1IFG : P1 interrupt flags
• P2IFG : P2 interrupt flags
13.1.3 General Purpose I/O DMA
When used as general purpose I/O pins, the
P0 and P1 ports are each associated with one
DMA trigger. These DMA triggers are IOC_0
for P0 and IOC_1 for P1 as shown in Table 37
on page 92.
The IOC_0 or IOC_1 DMA trigger is activated
when an input transition occurs on one of the
P0 or P1 pins respectively. Note input
transitions on pins configured as general
purpose I/O inputs only will produce the DMA
trigger.
13.1.4 Peripheral I/O
This section describes how the digital
input/output pins are configured as peripheral
I/Os. For each peripheral unit that can
interface with an external system through the
digital input/output pins, a description of how
peripheral I/Os are configured is given in the
following sub-sections.
In general, setting the appropriate PxSEL bits
to 1 is required to select peripheral I/O function
on a digital I/O pin.
Note that peripheral units have two alternative
locations for their I/O pins, refer to Table 36.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 70 of 232