CC2430 Datasheet, PDF (211/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Bit Name
Reset R/W Description
7:6 LOCK_THR[1:0]
5
CAL_DONE
4
CAL_RUNNING
3
LOCK_LENGTH
2
LOCK_STATUS
1:0 FREQ[9:8]
01
0
0
0
0
01
(2405
MHz)
R/W
Number of consecutive reference clock periods with
successful sync windows required to indicate lock:
00 : 64
01 : 128
10 : 256
11 : 512
R
Frequency synthesizer calibration done.
0 : Calibration not performed since the last time the FS was
turned on.
1 : Calibration performed since the last time the FS was
turned on.
R
Calibration status, '1' when calibration in progress.
R/W
LOCK_WINDOW pulse width:
0: 2 CLK_PRE periods
1: 4 CLK_PRE periods
R
PLL lock status
0 : PLL is not in lock
1 : PLL is in lock
R/W Frequency control word. Used directly in TX, in RX the LO
frequency is automatically set 2 MHz below the RF
frequency.
Frequency division = ^{2048 + FREQ[9 : 0]} ⇔
4
f_RF = (2048 + FREQ[9 : 0]) MHz
f_LO = (2048 + FREQ[9 : 0]− 2 ⋅ RXEN ) MHz
Table 60: Register FSCTRLH (0xDF10)
Bit Name
7:0 FREQ[7:0]
Reset R/W Description
0x65
(2405
MHz)
R/W
Frequency control word. Used directly in TX, in RX the LO
frequency is automatically set 2 MHz below the RF
frequency.
Frequency division = ^{2048 + FREQ[9 : 0]} ⇔
4
f_RF = (2048 + FREQ[9 : 0]) MHz
f_LO = (2048 + FREQ[9 : 0]− 2 ⋅ RXEN ) MHz
Table 61: Register FSCTRLL (0xDF11)
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 211 of 232