CC2430 Datasheet, PDF (66/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
12.9.8 Flash Programming
Programming of the on-chip flash is
performed via the debug interface. The
external host must initially send
instructions using the DEBUG_INSTR
debug command to perform the flash
programming with the Flash Controller as
described in section 13.14 on page 157.
12.10 RAM
The CC2430 contains static RAM. At
power-on the contents of RAM is
undefined. The RAM size is 8 KB in total.
The upper 4 KB of the RAM (XDATA
memory locations 0xF000-0xFFFF) retains
data in all power modes (see exception
below). The remaining lower 4 KB (XDATA
memory locations 0xE000-0xEFFF) will
loose its contents in PM2 and PM3 and
contains undefined data when returning to
PM0.
The memory locations 0xFD58-0xFEFF
consisting of 424 bytes in XDATA memory
space do not retain data when PM2/3 is
entered.
12.11 Flash Memory
The on-chip flash memory consists of
32768, 655536 or 131072 bytes. The flash
memory is primarily intended to hold
program code. The flash memory has the
following features:
• Flash page erase time: 20 ms
• Flash chip (mass) erase time: 20 ms
• Flash write time (4 bytes): 20 µs
• Data retention¹:100 years
• Program/erase endurance: 1,000
cycles
1 _{At room temperature}
The flash memory consists of the Flash
Main Page which is where the CPU reads
program code and data. The flash memory
also contains a Flash Information Page
which contains the Flash Lock Bits. The
Flash Information Page and hence the
Lock Bits is only accessed by first
selecting this page through the Debug
Interface. The Flash Controller (see
section 13.14) is used to write and erase
the contents of the flash memory.
When the CPU reads instructions from
flash memory, it fetches the next
instruction through a cache. The
instruction cache is provided mainly to
reduce power consumption by reducing
the amount of time the flash memory itself
is accessed. The use of the instruction
cache may be disabled with the
MEMCTR.CACHDIS register bit.
12.12 Memory Arbiter
The CC2430 includes a memory arbiter
which handles CPU and DMA access to all
memory space.
The control register MEMCTR is used to
control various aspects of the memory
sub-system. The MEMCTR register is
described below.
MEMCTR.MUNIF controls unified mapping
of CODE memory space as shown in
Figure 13 on page 38. Unified mapping is
required when the CPU is to execute
program stored in XDATA.
For the 128 KB flash version (CC2430-
F128), MEMCTR.FMAP1:0 controls
mapping of physical banks of the 128 KB
flash to the program address region
0x8000-0xFFFF in CODE memory space
as shown in Figure 14 on 23.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 66 of 232