CC2430 Datasheet, PDF (110/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
13.4 MAC Timer (Timer 2)
The MAC Timer is mainly used to provide
timing for 802.15.4 CSMA-CA algorithms
and for general timekeeping in the
802.15.4 MAC layer. When the MAC
Timer is used together with the Sleep
Timer described in section 13.5, the timing
function is provided even when the system
enters low-power modes.
The main features of the MAC Timer are
the following:
• 16-bit timer up-counter providing
symbol/frame period: 16µs/320µs
• Adjustable period with accuracy
31.25 ns
• 8-bit timer compare function
• 20-bit overflow count
• 20-bit overflow count compare
function
• Start of Frame Delimiter capture
function.
• Timer start/stop synchronous with
32.768 kHz clock and timekeeping
maintained by Sleep Timer.
• Interrupts generated on compare
and overflow
• DMA trigger capability
13.4.1 Timer Operation
This section describes the operation of the
timer.
13.4.1.1 General
After a reset the timer is in the timer IDLE
mode where it is stopped. The timer starts
running when T2CNF.RUN is set to 1. The
timer will then enter the timer RUN mode.
The entry is either immediate or it is
performed synchronous with the 32.768
kHz clock. See section 13.4.4 for a
description of the synchronous start and
stop mode.
Once the timer is running in RUN mode, it
can be stopped by writing a 0 to
T2CNF.RUN. The timer will then enter the
timer IDLE mode. The stopping of the
timer is performed either immediately or it
is performed synchronous with the 32.768
kHz clock
13.4.1.2 Up Counter
The MAC Timer contains a 16-bit timer,
which increments during each clock cycle.
13.4.1.3 Timer overflow
When the timer is about to count to a
value that is equal to or greater than the
timer period set by registers
T2CAPHPH:T2CAPLPL, a timer overflow
occurs. When the timer overflow occurs,
the timer value is set to the difference
between the value it is about to count to
and the timer period during the next clock
cycle. If the overflow interrupt mask bit
T2PEROF2.PERIM is 1, an interrupt
request is generated. The interrupt flag bit
T2CNF.PERIF is set to 1 regardless of the
interrupt mask value.
13.4.1.4 Timer delta increment
The timer period may be adjusted once
during a timer period by writing a timer
delta value. When a timer delta value is
written to the registers T2THD:T2TLD, the
16-bit timer halts at its current value and a
delta counter starts counting. The delta
counter starts counting from the delta
value written, down to zero. Once the delta
counter reaches zero, the 16-bit timer
starts counting again.
The delta counter decrements by the
same rate as the timer. When the delta
counter has reached zero it will not start
counting again until the delta value is
written once again. In this way a timer
period may be increased by the delta
value in order to make adjustments to the
timer overflow events over time.
13.4.1.5 Timer Compare
A timer compare occurs when the timer is
about to count to a value that is equal or
greater than the 8-bit compare value held
in the T2CMP register. Note that the
compare value is only 8 bits so the
compare is made between the compare
value and either the most significant byte
or the least significant byte of the timer.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 110 of 232