CC2430 Datasheet, PDF (111/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
The selection of which part of the timer is
to be compared is set by the
T2CNF.CMSEL bit.
When a timer compare occurs the interrupt
flag T2CNF.CMPIF is set to 1. An interrupt
request is also generated if the interrupt
mask T2PEROF2.CMPIM is set to 1.
13.4.1.6 Capture Input
The MAC timer has a timer capture
function which captures at the time when
the start of frame delimiter (SFD) status in
the radio goes high. Refer to sections 14.6
and 14.9 starting on page 170 for a
description of the SFD.
When the capture event occurs the current
timer value will be captured into the
capture register. The capture value can be
read
from
the
registers
T2CAPHPH:T2CAPLPL. The value of the
overflow count is also captured (see
section 13.4.1.7) at the time of the capture
event and can be read from the registers
T2PEROF2:T2PEROF1:T2PEROF0.
13.4.1.7 Overflow count
At each timer overflow, the 20-bit overflow
counter is incremented by 1. The overflow
counter value is read through the SFR
registers T2OF2:T2OF1:T2OF0. Note that
the register contents in T2OF2:T2OF1 is
latched when T2OF0 is read, meaning
that T2OF0 must always be read first.
Overflow count update
The overflow count value may be updated
by writing to the registers
T2OF2:T2OF1:T2OF0 when the timer is
IDLE.
Overflow count increment selection
The increment value for the overflow
counter can be set once by writing to the
T2OF2:T2OF1:T2OF0 registers when the
timer is in the RUN state. The value
written to these registers will be added to
the normal increment of 1 at the time of
the next overflow count increment i.e. at
the next timer overflow. The overflow
count increment will return to 1 at the
following increment.
13.4.1.8 Overflow count compare
A compare value may be set for the
overflow counter. The compare value is
set
by
writing
to
T2PEROF2:T2PEROF1:T2PEROF0.
When the overflow count value is equal or
greater than the set compare value an
overflow compare event occurs. If the
overflow compare interrupt mask bit
T2PEROF2.OFCMPIM is 1, an interrupt
request is generated. The interrupt flag bit
T2CNF.OFCMPIF is set to 1 regardless of
the interrupt mask value.
13.4.2 Interrupts
The Timer has three individually maskable
interrupt sources. These are the following:
• Timer overflow
• Timer compare
• Overflow count compare
The interrupt flags are given in the T2CNF
registers. The interrupt flag bits are set
only by hardware and may be cleared only
by writing to the SFR register.
Each interrupt source may be masked by
the mask bits in the T2PEROF2 register.
An interrupt is generated when the
corresponding mask bit is set, otherwise
the interrupt will not be generated. The
interrupt flag bit is set, however
disregarding the state of the interrupt
mask bit.
13.4.3 DMA Triggers
Timer 2 can generate two DMA triggers –
T2_COMP and T2_OVFL which are
activated as follows:
• T2_COMP: Timer 2 compare event
• T2_OVFL: Timer 2 overflow event
13.4.4 Timer start/stop synchronization
This section describes the synchronized
timer start and stop.
13.4.4.1 General
The Timer can be started and stopped
synchronously with the 32.768 kHz clock
rising edge. Note this event is derived from
a 32.768 kHz clock signal, but is
synchronous with the 32 MHz system
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 111 of 232