CC2430 Datasheet, PDF (93/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Table 38: DMA Configuration Data Structure
Byte Bit
Offset
0
7:0
1
7:0
2
7:0
3
7:0
4
7:5
4
4:0
5
7:0
6
7
6
6:5
6
4:0
7
7:6
7
5:4
Name
SRCADDR[15:8]
SRCADDR[7:0]
DESTADDR[15:8]
DESTADDR[7:0]
VLEN[2:0]
LEN[12:8]
LEN[7:0]
WORDSIZE
TMODE[1:0]
TRIG[4:0]
SRCINC[1:0]
DESTINC[1:0]
Description
The DMA channel source address, high
The DMA channel source address, low
The DMA channel destination address, high. Note that flash memory is not directly
writeable.
The DMA channel destination address, low. Note that flash memory is not directly
writeable.
Variable length transfer mode. In word mode, bits 12:0 of the first word is considered
as the transfer length.
000/111 Use LEN for transfer count
001
Transfer the number of bytes/words specified by first byte/word + 1 (up
to a maximum specified by LEN). Thus transfer count excludes length
byte/word
010
Transfer the number of bytes/words specified by first byte/word (up to a
maximum specified by LEN). Thus transfer count includes length
byte/word.
011
Transfer the number of bytes/words specified by first byte/word + 2 (up
to a maximum specified by LEN).
100
Transfer the number of bytes/words specified by first byte/word + 3 (up
to a maximum specified by LEN).
101
reserved
110
reserved
The DMA channel transfer count.
Used as maximum allowable length when VLEN = 000/111. The DMA channel
counts in words when in WORDSIZE mode, and in bytes otherwise.
The DMA channel transfer count.
Used as maximum allowable length when VLEN = 000/111. The DMA channel
counts in words when in WORDSIZE mode, and in bytes otherwise.
Selects whether each DMA transfer shall be 8-bit (0) or 16-bit (1).
The DMA channel transfer mode:
00 : Single
01 : Block
10 : Repeated single
11 : Repeated block
Select DMA trigger to use
00000 : No trigger (writing to DMAREQ is only trigger)
00001 : The previous DMA channel finished
00010 – 11111 : Selects one of the triggers shown in Table 37. The trigger is
selected in the order shown in the table.
Source address increment mode (after each transfer):
00 : 0 bytes/words
01 : 1 bytes/words
10 : 2 bytes/words
11 : -1 bytes/words
Destination address increment mode (after each transfer):
00 : 0 bytes/words
01 : 1 bytes/words
10 : 2 bytes/words
11 : -1 bytes/words
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 93 of 232