CC2430 Datasheet, PDF (161/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Table 40: Flash Lock Protection Bits Definition
Bit
Name
7:5
-
4
BBLOCK
3:1
LSIZE[2:0]
0
DBGLOCK
Description
Reserved, write as 0
Boot Block Lock
0
Page 0 is write protected
1
Page 0 is writeable, unless LSIZE is 000
Lock Size. Sets the size of the upper Flash area which is write-
protected. Byte sizes and page number are listed below
000 128k bytes (All pages) CC2430-F128 only
001 64k bytes (page 32 - 63) CC2430-F64/128 only
010 32k bytes (page 48 - 63)
011 16k bytes (page 56 - 63)
100 8k bytes (page 60 - 63)
101 4k bytes (page 62 - 63)
110 2k bytes (page 63)
111 0k bytes (no pages)
Debug lock bit
0
Disable debug commands
1
Enable debug commands
13.14.4 Flash Write Timing
The Flash Controller contains a timing
generator, which controls the timing
sequence of flash write and erase
operations. The timing generator uses the
information set in the Flash Write Timing
register, FWT.FWT[5:0], to set the
internal timing. FWT.FWT[5:0] must be
set to a value according to the currently
selected CPU clock frequency.
The value set in the FWT.FWT[5:0] shall
be set according to the CPU clock
frequency by the following equation.
FWT
=
21000 ∗ F_CPU
16 *10⁹
F_CPU is the CPU clock frequency. The
initial value held in FWT.FWT[5:0] after a
reset is 0x2A which corresponds to 32
MHz CPU clock frequency.
The FWT values for the 16 MHz and 32
MHz CPU clock frequencies are given in
Table 41.
CPU clock
frequency (MHz)
16
32
FWT
0x15
0x2A
Table 41: Flash timing (FWT) values
13.14.5 Flash DMA trigger
The Flash DMA trigger is activated when
flash data written to the FWDATA register
has been written to the specified location
in the flash memory, thus indicating that
the flash controller is ready to accept new
data to be written to FWDATA.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 161 of 232