CC2430 Datasheet, PDF (146/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
The timer interval is set by the
WDCTL.INT[1:0] bits. In timer mode, a
reset will not be produced when the timer
interval has been reached.
13.12.3 Watchdog Timer Example
Figure 33 shows an example of periodical
clearing of an active watchdog timer.
; clear watchdog timer
MOV WDCTL,#ABh
MOV WDCTL,#5Bh
Figure 33: WDT Example
13.12.4 Watchdog Timer Register
This section describes the register,
WDCTL, for the Watchdog Timer.
WDCTL (0xC9) – Watchdog Timer Control
Bit Name
7:4 _CLR[3:0]
3 _EN
2 _MODE
1:0 _INT[1:0]
Reset R/W
0000 R/W
0
R/W
0
R/W
00
R/W
Description
Clear timer. When 0xA followed by 0x5 is written to these bits, the
timer is loaded with 0x0. Note the timer will only be cleared when
0x5 is written within 0.5 watchdog clock period after 0xA was
written. Writing to these bits when EN is 0 have no effect. These
bits are always be read as 0000.
Enable timer. When a 1 is written to this bit the timer is enabled
and starts incrementing. Writing a 0 to this bit in timer mode stops
the timer. Writing a 0 to this bit in watchdog mode has no effect.
0 Timer disabled (stop timer)
1 Timer enabled
Mode select. This bit selects the watchdog timer mode.
0 Watchdog mode
1 Timer mode
Timer interval select. These bits select the timer interval defined as
a given number of 32.768 kHz oscillator periods.
00 clock period x 32768 (typical 1 s)
01 clock period x 8192 (typical 0.25 s)
10 clock period x 512 (typical 15.625 ms)
11 clock period x 64 (typical 1.9 ms)
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 146 of 232