CC2430 Datasheet, PDF (109/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control
Bit Name
7 _CPSEL
6 _IM
5:3 _CMP[2:0]
2 _MODE
1:0 _CAP[1:0]
Reset R/W
0
R/W
1
R/W
000
R/W
0
R/W
00
R/W
Description
Capture select. Timer 1 channel 2 captures on RF interrupt from
RF transceiver or capture input pin
0
Use normal capture input
1
Use RF interrupt from RF transceiver for capture
Channel 2 interrupt mask. Enables interrupt request when set.
Channel 2 compare mode select. Selects action on output when
timer value equals compare value in T1CC2
000 Set output on compare
001 Clear output on compare
010 Toggle output on compare
011 Set output on compare-up, clear on 0 (clear on compare-
down in up/down mode)
100 Clear output on compare-up, set on 0 (set on compare-
down in up/down mode)
101 _{Clear when equal T1CC0, set when equal T1CC2}
110 _{Set when equal T1CC0, clear when equal T1CC2}
111 Not used
Mode. Select Timer 1 channel 2 capture or compare mode
0
Capture mode
1
Compare mode
Channel 2 capture mode select
00 No capture
01 Capture on rising edge
10 Capture on falling edge
11 Capture on all edges
T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High
Bit Name
Reset R/W
7:0 _T1CC2[15:8] 0x00 R/W
Description
Timer 1 channel 2 capture/compare value, high order byte
T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low
Bit Name
7:0 _T1CC2[7:0]
Reset R/W
0x00 R/W
Description
Timer 1 channel 2 capture/compare value, low order byte
The TIMIF.OVFIM register bit resides in the TIMIF register, which is described together with
timer 3 and timer 4
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 109 of 232