CC2430 Datasheet, PDF (142/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
13.10.8 Power Management Registers
This section describes the Power
Management registers.
PCON (0x87) – Power Mode Control
Bit Name
7:2 _-
1_-
0 _IDLE
Reset
0x00
0
0
R/W
R/W
R0
R0/W
H0
Description
Not used.
Not used, always read as 0.
Power mode control. Writing a 1 to this bit forces CC2430 to enter
the power mode set by SLEEP.MODE. This bit is always read as
0
SLEEP (0xBE) – Sleep Mode Control
Bit Name
7
-
6 _{XOSC_STB}
5 _{HFRC_STB}
4:3 _RST[1:0]
2 _{OSC_PD}
1:0 _MODE[1:0]
Reset R/W
0
R0
0
R
0
R
XX
R
1
R/W
H0
00
R/W
Description
Unused
XOSC stable status:
0 – XOSC is not powered up or not yet stable
1 – XOSC is powered up and stable
HF RCOSC stable status:
0 – HF RCOSC is not powered up or not yet stable
1 – HF RCOSC is powered up and stable
Status bit indicating the cause of the last reset. If there are multiple
resets, the register will only contain the last event.
00 – Power-on reset
01 – External reset
10 – Watchdog timer reset
XOSC and HF RCOSC power down setting. The bit is cleared if
the CLKCON.OSC bit is toggled. Also, if there is a calibration in
progress and the CPU attempts to set the bit, the bit will be
updated at the end of calibration:
0 – Both oscillators powered up
1 – Oscillator not selected by CLKCON.OSC bit powered down
Sleep mode setting:
00 – Power mode 0
01 – Power mode 1
10 – Power mode 2
11 – Power mode 3
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 142 of 232