CC2430 Datasheet, PDF (72/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
• RT : RTS
• CT : CTS
SPI:
• MI : MISO
• MO : MOSI
• C : SCK
• SS : SSN
P2DIR.PRIP0 selects the order of
precedence when assigning several
peripherals to port 0. When set to 01, USART1
has precedence. Note that if UART mode is
selected and hardware flow control is disabled,
USART0 or timer 1 will have precedence to
use ports P0_2 and P0_3.
P2SEL.PRI3P1 and P2SEL.PRI2P1 select
the order of precedence when assigning
several peripherals to port 1. USART1 has
precedence when the former is set to 1 and
the latter is set to 0. Note that if UART mode is
selected and hardware flow control is disabled,
USART0 or timer 3 will have precedence to
use ports P2_4 and P2_5.
13.1.4.3 Timer 1
PERCFG.T1CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 36, the Timer 1 signals are shown as
the following:
• 0 : Channel 0 capture/compare pin
• 1 : Channel 1 capture/compare pin
• 2 : Channel 2 capture/compare pin
P2DIR.PRIP0 selects the order of
precedence when assigning several
peripherals to port 0. When set to 10 or 11 the
timer 1 channels have precedence.
P2SEL.PRI1P1 and P2SEL.PRI0P1 select
the order of precedence when assigning
several peripherals to port 1. The timer 1
channels have precedence when the former is
set low and the latter is set high.
13.1.4.4 Timer 3
PERCFG.T3CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 36, the Timer 3 signals are shown as
the following:
• 0 : Channel 0 capture/compare pin
• 1 : Channel 1 capture/compare pin
P2SEL.PRI2P1 selects the order of
precedence when assigning several
peripherals to port 1. The timer 3 channels
have precedence when the bit is set.
13.1.4.5 Timer 4
PERCFG.T4CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 36, the Timer 4 signals are shown as
the following:
• 0 : Channel 0 capture/compare pin
• 1 : Channel 1 capture/compare pin
P2SEL.PRI1P1 selects the order of
precedence when assigning several
peripherals to port 1. The timer 4 channels
have precedence when the bit is set.
13.1.5 ADC
When using the ADC in an application, Port 0
pins must be configured as ADC inputs. Up to
eight ADC inputs can be used. To configure a
Port 0 pin to be used as an ADC input the
corresponding bit in the ADCCFG register must
be set to 1. The default values in this register
select the Port 0 pins as non-ADC input i.e.
digital input/outputs.
The settings in the ADCCFG register override
the settings in P0SEL.
The ADC can be configured to use the
general-purpose I/O pin P2_0 as an external
trigger to start conversions. P2_0 must be
configured as a general-purpose I/O in input
mode, when being used for ADC external
trigger.
Refer to section 13.7 on page 127 for a
detailed description of use of the ADC.
13.1.6 Debug interface
Ports P2_1 and P2_2 are used for debug data
and clock signals, respectively. These are
shown as DD (debug data) and DC (debug
clock) in Table 36. When the debug interface
is in use, P2DIR should select these pins as
inputs. The state of P2SEL is overridden by the
debug interface. Also, the direction is
overridden when the chip changes the
direction to supply the external host with data.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 72 of 232