CC2430 Datasheet, PDF (40/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
12.3.2 Memory Space
This section describes the details of each CPU
memory space.
XDATA memory space. The XDATA memory
map is given for each flash memory option in
Figure 7, Figure 10 and Figure 13. For the
devices with flash size above 32 KB, the lower
55 KB of the flash program memory is mapped
into the address range 0x0000-0xDEFF. For
the 32 KB flash size option, the 32 KB flash
memory is mapped to 0x0000-0x7FFF in
XDATA memory space. Access to
unimplemented areas shown as shaded in the
memory map gives an undefined result.
For all devices, the 8 KB SRAM is mapped into
address range 0xE000-0xFFFF, and the SFR
registers into address range 0xDF80-0xDFFF.
This allows the DMA controller and the CPU
access to all the physical memories in a single
unified address space.
One of the ramifications of this mapping is that
the first address of usable SRAM starts at
address 0xE000 instead of 0x0000, and
therefore compilers/assemblers must take this
into consideration.
In low-power modes PM2-3, with the lowest
power consumption, the upper 4 KB of SRAM
i.e. the memory locations in XDATA address
range 0xF000-0xFFFF will retain their
contents. Refer to section 13.10 on page 140
for a detailed description of power modes and
SRAM data retention.
CODE memory space. The CODE memory
space uses either a unified or non-unified
mapping to the physical memories as shown in
Figure 8 - Figure 9, Figure 11 - Figure 12 and
Figure 14- Figure 15. The unified mapping of
the CODE memory space is similar to the
XDATA mapping. Note that there is the
exception that SFR registers internal to the
CPU can not be accessed (see section 12.4
on page 43).
With flash memory sizes above 32 KB, the
lower 55 KB of flash memory is mapped to
CODE memory space when unified mapping is
used. This is similar to the XDATA memory
space.
The 8 KB SRAM is included in the CODE
address space to allow program execution out
of the SRAM.
Note: in order to use the unified memory
mapping within CODE memory space, the
SFR register bit MEMCTR.MUNIF must be 1.
For devices with flash memory size of 128 KB
(CC2430-F128), a memory banking scheme is
used for the CODE memory space. Since the
physical memory size is 128 KB, the upper 32
KB area of CODE memory space is mapped to
one out of the four 32 KB physical banks of
flash memory through the flash bank select
bits as shown in the non-unified CODE
memory map. The flash bank select bits reside
in the SFR register bits MEMCTR.FMAP (see
section 12.12 on page 66). When unified
CODE memory space mapping is used, the
CODE memory is mapped to the flash memory
in a similar manner to non-unified mapping,
using memory banking, however 23 KB of the
selected bank is available, as shown in the
memory map.
Access to unimplemented areas shown as
shaded in the memory map gives an
undefined result.
DATA memory space. The 8-bit address
range of DATA memory is mapped into the
upper 256 bytes of the 8 KB SRAM. This area
is also accessible through the CODE and
XDATA memory spaces at the address range
0xFF00-0xFFFF.
SFR memory space. The 128 entry hardware
register area is accessed through this memory
space. The SFR registers are also accessible
through the XDATA/DMA address space at the
address range 0xDF80-0xDFFF. Some CPU-
specific SFR registers reside inside the CPU
core and can only be accessed using the SFR
memory space and not through the duplicate
mapping into XDATA memory space.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 40 of 232