CC2430 Datasheet, PDF (148/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
The number of stop bits to be transmitted
is set to one or two bits determined by the
register bit UxUCR.SPB. The receiver will
always check for one stop bit. If the first
stop bit received during reception is not at
the expected stop bit level, a framing error
is signaled by setting register bit
UxCSR.FE high. UxCSR.FE is cleared
when UxCSR is read. The receiver will
check both stop bits when UxUCR.SPB is
set.
13.13.2 SPI Mode
This section describes the SPI mode of
operation for synchronous communication.
In SPI mode, the USART communicates
with an external system through a 3-wire
or 4-wire interface. The interface consists
of the pins MOSI, MISO, SCK and SS_N.
Refer to section 13.1 for description of
how the USART pins are assigned to the
I/O pins.
The SPI mode includes the following
features:
• 3-wire (master) and 4-wire SPI
interface
• Master and slave modes
• Configurable SCK polarity and phase
• Configurable LSB or MSB first transfer
The SPI mode is selected when
UxCSR.MODE is set to 0.
In SPI mode, the USART can be
configured to operate either as an SPI
master or as an SPI slave by writing the
UxCSR.SLAVE bit.
13.13.2.1 SPI Master Operation
An SPI byte transfer in master mode is
initiated when the UxDBUF register is
written. The USART generates the SCK
serial clock using the baud rate generator
(see section 13.13.3) and shifts the
provided byte from the transmit register
onto the MOSI output. At the same time
the receive register shifts in the received
byte from the MISO input pin.
The UxCSR.ACTIVE bit goes high when
the transfer starts and low when the
transfer ends. When the transfer ends, the
UxCSR.RX_BYTE and UxCSR.TX_BYTE
bits are set to 1. A receive interrupt is
generated when new received data is
ready in the UxDBUF USART
Receive/Transmit Data register.
The polarity and clock phase of the serial
clock SCK is selected by UxGCR.CPOL
and UxGCR.CPHA. The order of the byte
transfer is selected by the UxGCR.ORDER
bit.
At the end of the transfer, the received
data byte is available for reading from the
UxDBUF.
A transmit interrupt is generated when the
unit is ready to accept another data byte
for transmission. Since UxDBUF is double-
buffered, this happens just after the
transmission has been initiated.
13.13.2.2 SPI Slave Operation
An SPI byte transfer in slave mode is
controlled by the external system. The
data on the MOSI input is shifted into the
receive register controlled by the serial
clock SCK which is an input in slave
mode. At the same time the byte in the
transmit register is shifted out onto the
MISO output.
The UxCSR.ACTIVE bit goes high when
the transfer starts and low when the
transfer ends. Then the UxCSR.RX_BYTE
and UxCSR.TX_BYTE bits are set and a
receive interrupt is generated.
The expected polarity and clock phase of
SCK is selected by UxGCR.CPOL and
UxGCR.CPHA. The expected order of the
byte transfer is selected by the
UxGCR.ORDER bit.
At the end of the transfer, the received
data byte is available for reading from
UxDBUF
The transmit interrupt is generated at the
start of the operation.
13.13.3 SSN Slave Select Pin
When the USART is operating in SPI
mode, configured as an SPI slave, the
Slave Select (SSN) pin is an input to the
SPI. When SSN is held low, the SPI slave
is active and receives data on the MOSI
input and outputs data on the MISO
output. When SSN is held high, the SPI
slave is inactive and will not receive data.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 148 of 232