CC2430 Datasheet, PDF (112/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
clock and thus has a period approximately
equal the 32.768 kHz clock period.
At the time of a synchronous start the
timer is reloaded with new calculated
values for the timer and overflow count
such that it appears that the timer has not
been stopped.
13.4.4.2 Timer synchronous stop
After the timer has started running, i.e.
entered timer RUN mode it is stopped
synchronously by writing 0 to T2CNF.RUN
when T2CNF.SYNC is 1. After T2CNF.RUN
has been set to 0, the timer will continue
running until the 32.768 kHz clock rising
edge is sampled as 1. When this occurs
the timer is stopped and the current Sleep
timer value is stored.
13.4.4.3 Timer synchronous start
When the timer is in the IDLE mode it is
started synchronously by writing 1 to
T2CNF.RUN when T2CNF.SYNC is 1. After
T2CNF.RUN has been set to 1, the timer
will remain in the IDLE mode until the
32.768 kHz clock rising edge is detected.
When this occurs the timer will first
calculate new values for the 16-bit timer
value and for the 20-bit timer overflow
count, based on the current and stored
Sleep timer values and the current 16-bit
timer values. The new MAC Timer and
overflow count values are loaded into the
timer and the timer enters the RUN mode.
This synchronous start process takes 75
clock cycles from the time when the
32.768 kHz clock rising edge is sampled
high. The synchronous start and stop
function requires that the system clock
frequency is selected to be 32 MHz. If the
16 MHz clock is selected, there will be an
offset added to the new calculated value.
The method for calculating the new MAC
Timer value and overflow count value is
given below. Due to the fact that the MAC
Timer clock and Sleep timer clocks are
asynchronous with a non-integer clock
ratio there will be an error of maximum ±1
in calculated timer value compared to the
ideal timer value.
Calculation of new timer value and
overflow count value
N_c = CurrentSleepTimerValue
N _s = StoredSleepTimerValue
K_ck = ClockRatio = 976.5625 ⁴
stw = SleepTimerWidth = 24
P = Timer2Period
O_c = CurrentOverflowCountValue
T_c = CurrentTimerValue
T_OH = Overhead = 75
N_t = N_c − N_s
N_t ≤ 0 ⇒ N_d = 2^stw + N_t ; N_t > 0 ⇒ N_d = N_t
C = N_d ⋅ K_ck + T_C + T_OH (Rounded to
nearest integer value)
T = C mod P
O
=
(C
−
P
T
)
+
O_C
Timer2Value = T
Timer2OverflowCount = O
13.4.5 Timer 2 Registers
The SFR registers associated with Timer 2
are listed in this section. These registers
are the following:
• T2CNF – Timer 2 Configuration
• T2HD – Timer 2 Count/Delta High
• T2LD – Timer 2 Count/Delta Low
• T2CMP – Timer 2 Compare
• T2OF2 – Timer 2 Overflow Count 2
• T2OF1 – Timer 2 Overflow Count 1
• T2OF0 – Timer 2 Overflow Count 0
4 _{Clock ratio of MAC Timer clock}
frequency (32 MHz) and Sleep timer clock
frequency (32.768 kHz)
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 112 of 232