CC2430 Datasheet, PDF (113/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
• T2CAPHPH – Timer 2 Capture/Period
High
• T2CAPLPL – Timer 2 Capture/Period
Low
• T2PEROF2 – Timer 2 Overflow
Compare/Capture 2
• T2PEROF1 – Timer 2 Overflow
Compare/Capture 1
• T2PEROF0 – Timer 2 Overflow
Compare/Capture 0
T2CNF (0xC3) – Timer 2 Configuration
Bit Name
7 _CMPIF
Reset
0
R/W
R/W0
6 _PERIF
0
R/W0
5 _OFCMPIF
0
R/W
4
-
3 _CMSEL
0
R0
0
R/W
2
-
1 _SYNC
0
R/W
1
R/W
0
RUN
0
R/W
Description
Timer compare interrupt flag. This bit is set to 1 when a timer compare
event occurs. Cleared by software only. Writing a 1 to this bit has no
effect.
Overflow interrupt flag. This bit is set to 1 when a period event occurs.
Cleared by software only. Writing a 1 to this bit has no effect.
Overflow compare interrupt flag. This bit is set to 1 when a overflow
compare occurs. Cleared by software only. Writing a 1 to this bit has no
effect.
Not used. Read as 0
Timer compare source select.
0 Compare with 16-bit Timer bits [15:8]
1 Compare with 16-bit Timer bits [7:0]
Reserved. Always set to 0
Enable synchronized start and stop.
0 start and stop of timer is immediate
1 start and stop of timer is synchronized with 32.768 kHz edge and new
timer values are reloaded.
Start timer. Writing this bit shall start or stop the timer. When reading
this bit the current state of the timer is returned.
0 stop timer (IDLE state)
1 start timer (RUN state)
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 113 of 232