CC2430 Datasheet, PDF (159/234 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
13.14.1.2 CPU Flash Write
The CPU can also write directly to the
flash. The CPU writes data to the Flash
Write Data register, FWDATA. The flash
memory is written each time four bytes
have been written to FWDATA. The CPU
can poll the FCTL.SWBSY status to
determine when the flash is ready for four
more bytes to be written to FWDATA
Performing flash write from XDATA
The steps required to start a flash write
operation from XDATA are shown in
Figure 35 on page 159.
Disable interrupts
YES
BUSY=1?
NO
Setup FCTL, FWT,
FADDRH, FADDRL
Write FWDATA
; Write 32-bit word from XDATA
; Assumes 32 MHz system clock is used
;
CLR EA
;mask interrupts
C1: MOV A,FCTL
;wait until flash controller is ready
JB
ACC.7,C1
MOV FADDRH,#00h
;setup flash address high
MOV FADDRL,#01h
;setup flash address low
MOV FWT,#2Ah
;setup flash timing
MOV FCTL,#02h
;set flash page write
MOV FWDATA,#12h
;first byte
MOV FWDATA,#34h
;second byte
MOV FWDATA,#56h
;third byte
MOV FWDATA,#78h
;fourth byte, initiates write
Figure 35: Flash write performed from XDATA
13.14.2 Flash Page Erase
A page erase is initiated by setting
FCTL.ERASE to 1. The page addressed
by FADDRH[6:1] is erased when a page
erase is initiated. Note that if a page erase
is initiated simultaneously with a page
write, i.e. FCTL.WRITE is set to 1, the
page erase will be performed before the
page write operation. The FCTL.BUSY bit
can be polled to see when the page erase
has completed.
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 159 of 232